KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
In: Formal Methods in Computer Aided Design (FMCAD); (2019-10-01) S. 105-109
Konferenz
Zugriff:
Titel: |
KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design
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Autor/in / Beteiligte Person: | Piccolboni, Luca ; Guglielmo, Giuseppe Di ; Carloni, Luca P. |
Quelle: | Formal Methods in Computer Aided Design (FMCAD); (2019-10-01) S. 105-109 |
Veröffentlichung: | 2019 |
Medientyp: | Konferenz |
ISBN: | 978-0-9835678-9-9 (print) |
ISSN: | 2642-732X (print) |
DOI: | 10.23919/FMCAD.2019.8894295 |
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