Reduced Power Combinational Logics in 16nm CMOS Technology
In: 8th International Conference on Signal Processing and Integrated Networks (SPIN); (2021-08-26) S. 1008-1011
Konferenz
Zugriff:
Titel: |
Reduced Power Combinational Logics in 16nm CMOS Technology
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Autor/in / Beteiligte Person: | Singh, Himanshu ; Singhal, Smita ; Mehra, Anu ; Mudga, Aditya |
Quelle: | 8th International Conference on Signal Processing and Integrated Networks (SPIN); (2021-08-26) S. 1008-1011 |
Veröffentlichung: | 2021 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-3564-2 (print) ; 978-1-6654-3563-5 (print) |
ISSN: | 2688-769X (print) |
DOI: | 10.1109/SPIN52536.2021.9566109 |
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