VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits
In: ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems; Jg. 2 (2001) S. 723-727
Konferenz
Zugriff:
Titel: |
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits
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Autor/in / Beteiligte Person: | Perri, S. ; Corsonello, P. ; Cocorullo, G. ; Cappuccino, G. ; Staino, G. |
Quelle: | ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems; Jg. 2 (2001) S. 723-727 |
Veröffentlichung: | 2001 |
Medientyp: | Konferenz |
ISBN: | 0-7803-7057-0 (print) ; 978-0-7803-7057-9 (print) |
DOI: | 10.1109/ICECS.2001.957577 |
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