A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align
In: 6th International Conference on Integrated Circuits and Microsystems (ICICM); (2021-10-22) S. 171-174
Konferenz
Zugriff:
Titel: |
A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align
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Autor/in / Beteiligte Person: | Zhang, Hongguang ; Zhang, Zhiqiang ; Gong, Yuanyuan ; Zhang, Yanan ; Jung, Jake ; Lee, Brian ; Kim, Edwin ; Cao, Kanyu |
Quelle: | 6th International Conference on Integrated Circuits and Microsystems (ICICM); (2021-10-22) S. 171-174 |
Veröffentlichung: | 2021 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-5886-3 (print) ; 978-1-6654-5885-6 (print) |
DOI: | 10.1109/ICICM54364.2021.9660276 |
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