A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 42 (2023), Heft 1, S. 122-135
Online
academicJournal
Zugriff:
Titel: |
A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System
|
---|---|
Autor/in / Beteiligte Person: | Zhao, W. ; Xu, J. ; Wei, X. ; Wu, B. ; Wang, C. ; Zhu, W. ; Tong, W. ; Feng, D. ; Liu, J. |
Link: | |
Zeitschrift: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 42 (2023), Heft 1, S. 122-135 |
Veröffentlichung: | 2023 |
Medientyp: | academicJournal |
ISSN: | 0278-0070 (print) ; 1937-4151 (print) |
DOI: | 10.1109/TCAD.2022.3169458 |
Sonstiges: |
|