DDR interface modeling and chip decoupling capacitance optimization through jitter simulation
In: IEEE 26th Workshop on Signal and Power Integrity (SPI); (2022-05-22) S. 1-4
Konferenz
Zugriff:
Titel: |
DDR interface modeling and chip decoupling capacitance optimization through jitter simulation
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Autor/in / Beteiligte Person: | Peyrard, Marie ; Marais, Dominique ; Duperthuy, Xavier ; Froidevaux, Nicolas ; Jacquemod, Gilles |
Quelle: | IEEE 26th Workshop on Signal and Power Integrity (SPI); (2022-05-22) S. 1-4 |
Veröffentlichung: | 2022 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-8625-5 (print) |
DOI: | 10.1109/SPI54345.2022.9874934 |
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