On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
In: 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI); (2022-08-22) S. 1-6
Konferenz
Zugriff:
Titel: |
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
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Autor/in / Beteiligte Person: | Knorst, Tiago ; Korol, Guilherme ; Jordan, Michael Guilherme ; Vicenzi, Julio Costella ; Lorenzon, Arthur ; Rutzig, Mateus Beck ; Beck, Antonio Carlos Schneider |
Quelle: | 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI); (2022-08-22) S. 1-6 |
Veröffentlichung: | 2022 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-8128-1 (print) |
DOI: | 10.1109/SBCCI55532.2022.9893223 |
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