Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model
In: Electronics (Basel), Jg. 13 (2024-04-01), Heft 7
Online
academicJournal
Zugriff:
Titel: |
Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model
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Autor/in / Beteiligte Person: | Yu, Yihe ; Pan, Wanyuan ; Tang, Chengcheng ; Yin, Ningyuan ; Yu, Zhiyi |
Link: | |
Zeitschrift: | Electronics (Basel), Jg. 13 (2024-04-01), Heft 7 |
Veröffentlichung: | 2024 |
Medientyp: | academicJournal |
ISSN: | 2079-9292 (print) |
DOI: | 10.3390/electronics13071284 |
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