An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS
Institute of Electrical & Electronics Engineers (IEEE), 2011
Online
academicJournal
Zugriff:
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Reducing power consumption requires the development of system-on-chip implementations that must provide both energy efficiency and adequate performance to meet the demands of the long deployment lifetimes and bursts of computation that characterize wireless sensor network (WSN) applications. Therefore, this work argues that designers should evaluate the design in terms of average power for an entire workload, including active and idle periods, not just the metric of energy-per-instruction.
Engineering and Applied Sciences
Titel: |
An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS
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Autor/in / Beteiligte Person: | Hempstead, Mark ; Brooks, David M. ; Wei, Gu-Yeon |
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Veröffentlichung: | Institute of Electrical & Electronics Engineers (IEEE), 2011 |
Medientyp: | academicJournal |
ISSN: | 2156-3357 (print) |
DOI: | 10.1109/JETCAS.2011.2160751 |
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