Technique for Designing High Speed Noise Immune CMOS Domino High Fan-in Circuits
In: International Journal of Engineering and Management Research (IJEMR), Jg. 7 (2017-09-10), Heft 5, S. 178-190
academicJournal
Zugriff:
Titel: |
Technique for Designing High Speed Noise Immune CMOS Domino High Fan-in Circuits
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Autor/in / Beteiligte Person: | Lakshmi, A. Chaitanya ; Nausheen, Saba ; Renuka, M. |
Zeitschrift: | International Journal of Engineering and Management Research (IJEMR), Jg. 7 (2017-09-10), Heft 5, S. 178-190 |
Veröffentlichung: | 2017 |
Medientyp: | academicJournal |
ISSN: | 2394-6962 (print) ; 2250-0758 (print) |
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