Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
In: Theses and Dissertations
Online
Hochschulschrift
Zugriff:
This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.
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Design of a High Speed Mixed Signal CMOS Mutliplying Circuit
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Autor/in / Beteiligte Person: | Bartholomew, David Ray |
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Zeitschrift: | Theses and Dissertations |
Veröffentlichung: | BYU ScholarsArchive. |
Medientyp: | Hochschulschrift |
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