High-speed and multi-bitrate clock and data recovery system based on half-rate clocking
In: alephsysno: 002271544; proquestno: AAIMR22648; Theses scanned by UMI/ProQuest.; (2005)
Hochschulschrift
Zugriff:
Today's telecommunications infrastructures and consumer electronics rely largely on serial communications. Serial communications is a major form of transmitting information; therefore, faster and more cost effective methods of designing receivers are becom ing interesting research topics ([1]-[8]). This work focuses on the full design flow of an integrated clock and data recovery (CDR) system in CMOS technology, responding to this need of high-speed and cost effective circuit solutions.
This thesis reports a full bottom-up design flow of a CDR system. The main challenge is to use an affordable and mainstream technology, such as the CMOS 0.18-micron technology, to implement a 6-Gbps serial receiver for land line applications. Unfortunately, the traditional full rate implementation is impossible with this CMOS technology; therefore, this problem is alleviated by exploring half-rate architectures.
The basic building blocks were first designed using TSMC's CMOS 0.18-micron technology. These gates were then assembled to create larger circuit blocks such as an edge-triggered flip flop, a double edge-triggered flip flop, a phase detectors, a phase/frequency detector, etc. Each component was characterized and then verified. The completely assembled system was simulated, verified, and then sent for fabrication. Finally, the system was tested and verified for analysis.
Eye diagram patterns were extracted from the CDR prototype circuit. Results show an opening in the eye, which suggests that the data pattern are properly recovered. The system was also successfully tested for lower bit rates. A top-down verification method was then executed in order to compare the experimental and simulation results.
The main contribution of this work is the full detailed documentation of the design flow of a CDR system using a bottom-up implementation with a top-down verification methodology. Verification methods were designed and applied in order to investigate some discrepancies in the results.
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High-speed and multi-bitrate clock and data recovery system based on half-rate clocking
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Autor/in / Beteiligte Person: | Hong, Sung-Hwan (David), 1978 |
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Quelle: | alephsysno: 002271544; proquestno: AAIMR22648; Theses scanned by UMI/ProQuest.; (2005) |
Veröffentlichung: | McGill University, 2005 |
Medientyp: | Hochschulschrift |
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