DSP Processor Approaches for The Synchronization Loop in DMT-Based VDSL

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This thesis first discusses the principles and specifications of the DMT technique according to the drafts of the Very high-speed Digital Subscriber Lines (VDSL) standards. We focus on the implementations of the fast Fourier transform (FFT), the symbol synchronization, and the sample synchronization in the synchronization loop using DSP processor approach. After comparing various algorithms, Radix-2 algorithm is used to do the fast Fourier transform, Maximum Likelihood method is used to do the symbol synchronization, and all digital structure is used to do the sample synchronization. The complexity is analyzed with the parameterized digital signal processor (NCU_DSP). The evaluated result concludes that we need about 24 NCU_DSP processors to realize the synchronization loop and 6 NCU_DSP processors if FFT is implemented by ASIC. This thesis also proposes one novel method to solve the errors occurred in the reduced-width multiplier. The main concept of the method is to use an input-number-dependent compensation vector to replace the unnecessary computations in the standard multipliers. The module generator of our proposed method (reduced-width multipliers) is developed. It can automatically generate the C code for the system simulation and the synthesizable Verilog code for the hardware design. The proposal is also successfully applied in pulse-shaping filters of a QAM mode CATV transceiver. The comparison result shows that 50.04% of the hardware area and 33.82% of the critical path delay can be saved while comparing with the post truncation method.