Implementation of a Dual Mips-like Core Chip
2007
Hochschulschrift
Zugriff:
95
This study implements a 32-b RISC microprocessor of dual MIPS-like core chip by using algorithmic state machine (ASM)and Verilog hardware description language. The overall design is simulated by using SynaptiCAD, programmed to FPGA chip by using Xilinx ISE 7.1, synthesized and IC layouted by using Cadence BuildGates and SOC Encounter, respectively. The developed architecture of dual-core chip with enhanced performance, validated by control circuit of a stepper motor, can applied to more applications such as robot control and image processing, etc.
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Implementation of a Dual Mips-like Core Chip
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Autor/in / Beteiligte Person: | Tung Han Hsieh ; 謝東翰 |
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Veröffentlichung: | 2007 |
Medientyp: | Hochschulschrift |
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