The Study of Wrapped-Select-Gate SONOS Memory with Split-Control- Gate in NAND Array

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For the first time, we propose the novel Wrapped-Select Gate SONOS (WSG-SONOS) memory with split-control gate in NAND architecture. The memory process is not only simple but also compatible with embedded non-volatile memory in conventional standard logic CMOS products. In this thesis, we demonstrate the physical mechanism and elimination of 2nd bit effect in 2 bit/cell operation. The results show that non-ideal 2nd bit effect would not be a consideration for the novel WSG-SONOS memory device with multi-level operation. It effectively increases the reliability of memory cell for the larger sensing margin of each state. Moreover, we operate the WSG-SONOS memory in 2 bit/cell mode with multi-level operation. The programming and erasing operations are performed by the Source-Side Injection (SSI) and Band-to-Band Tunneling Hot-Hole (BTBTHH), respectively. While operating the memory device in multi-level mode, the slowest program speed would be still less than 30us; the programming current is about 80nA as the wrapped-select gate voltage and word-line gate voltage are 0.45V and 11V, respectively. The fastest erase speed of 8ms is achieved. The main features of this novel device contain the wrapped-select gate and split-control gate. By utilizing the wrapped-select gate to be an assistance gate, the SSI could accomplish the precisely multi-level operation in this memory cell. The SSI programming operation would achieve the low power consumption and high program speed’s characteristics in the memory device. In addition, the split-control gate could effectively decrease the variation of threshold voltage by eliminating the 2nd bit effect disturbance. It would remain the sense margin in this novel memory with multi-level operation. Moreover, the optimum thickness of ONO stack performs excellently for almost no gate disturbance, no read disturbance and long data retention. Even after 10K P/E cycling stress, the error bit wouldn’t happen in such device’s sensing window. As a result, the WSG-SONOS memory with split-control gate in NAND array is very adapted for the 2 bit/cell mode with multi-level operation. It owns the high program speed, low power consumption and high reliability characteristics for the flash memory technology demands. Thus, it has the larger application potential for flash memory market in the future.