Design of Low Power Dual-Path PS-LDPC Decoder

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In this thesis, a design of low power high throughput dual-path PS-LDPC decoder is presented. The (512, 1024) check matrix is a regular matrix whose column weight and row weight are 3 and 6, respectively. There are four units including a variable node unit (VNU), a check node unit (CNU), and two message storage units. The message storage unit is composed of shift registers and multiplexers. The min-sum algorithm was applied in the CNU. With the specially designed PS-LDPC code, the proposed partial parallel architecture using shift registers instead of demultiplexers and registers for message storage can reduce the hardware cost, routing congestion and critical path delay, which resulting lower power consumption. During decoding process of the traditional decoding method, CNU and VNU operations are active alternatively in every decoding iteration. To increase the throughput, these idled CNU and VNU circuit blocks can be utilized more efficiently by the dual-path data flow approach. Therefore, the throughout is increased to almost two times. After implemented with TSMC 0.18μm CMOS process, the proposed decoder can achieve the decoding throughput of 2.844Gbps at the clock frequency of 100MHz. The chip size is 10.80mm^2, the core size is 5.18mm^2 and the average power consumption with the supply voltage of 1.62V is 571.5mW.