Design and Implementation of Low-Complexity Soft-Output K-Best MIMO Detector
2016
Hochschulschrift
Zugriff:
104
This thesis investigates system integration of multiple input multiple output (MIMO) with low density parity check (LDPC) codeing/decoding for applications in wireless communication systems. In order to make the LDPC decoder reaching its decoding performance, a low-complexity and low-power MIMO detector with soft outputs for LDPC decoders was designed and implemented. In this thesis, the random generated channel matrices H are normalized in simulations to avoid the same noise but having different influences to the signals in different channel matrices. The K-Best algorithm with K = 8 for the signal detector was used in 64-QAM modulation systems. The algorithm combines the characteristics of the breadth-first and depth-first methods with constant throughput. Besides, enumeration circuits are employed for signal estimation to simplify the hardware. For the soft outputs of MIMO detector, the algorithm named Early Stage Decision (ESD) to generate log likelihood ratios (LLR) is proposed. In comparison with the other algorithms ocurring error floors at high signal-to-noise ratio (SNR) situations, ESD algorithm allows the LDPC decoders to achieve excellent decoding performance at high SNR conditions, and hardware complexity is lower than those of the others. In hardware design, in order to reduce the amount of computations for sorting and the cost of hardware, two circuits are adopted for sorting. One is 32 TO 8 selecting circuits, and the other is 8 TO 8 sorting circuits. Both of them with the ESD algorithm can enhance hardware utilization efficiency. The goal of design is to control pipeline stages and maximize throughput by selecting appropriate pipeline stages to reduce registers and hardware area as well. Since the computation is evenly distributed between registers, the high-speed partial parallel MIMO detector is obtained. This system was implemented for 44 antenna with 64-QAM modulation. In the case of high SNR conditions, this system still has good decoding performance, and the bit error rate (BER) is declined continiously using Matlab simulations. When SNR = 24 dB, the BER can be as low as 10-7. This MIMO detector was verified using Xilinx Virtex-7 XCVX330T FPGA. The implementation results show that it works at 119 MHz and the throughput can be up to 714 Mbps. This design was also designed using TSMC 90nm process. The maximum throughput is 726 Mbps at the frequency of 121 MHz. The gate count is about 587K with power consumption of 50.8mW.
Titel: |
Design and Implementation of Low-Complexity Soft-Output K-Best MIMO Detector
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Autor/in / Beteiligte Person: | Lin, Shung-Ru ; 林尚儒 |
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Veröffentlichung: | 2016 |
Medientyp: | Hochschulschrift |
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