Real-time High Definition Video Decoder Based on Digital Signal Processors

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To upgrade the newest high efficiency video coding (HEVC) standard used in heterogeneous access networks, the JCT-VC has been approved scalable extension of HEVC (SHVC) in July 2014. Based on the HEVC, the SHVC scheme supports multi-loop solutions by enabling different inter-layer prediction mechanisms. In multi-loop architecture, a full decoding loop takes place in every intermedia layer needed to decode a target layer. Although the multi-loop decoding architecture can achieve higher coding efficiency than the single-loop decoding architecture, it increases the decoded picture buffer (DPB) size and memory bandwidth for motion compensation (MC) on the decoder side. This leads to the reduction of decoded performance for SHVC. In order to speed up the SHVC decoding process and increase decoding performance, we propose three researching directions to achieve the requirement in this dissertation. Firstly, we propose a dynamic DPB assignment algorithm (DDPBAA) to improve the fixed size of DPB. We design a DPB manager (DPBM) to control and storage the parameters and encoding data. Secondly, in order to finish a real-time SHVC decoder on software based on multi-cores CPU, a parallel processing architecture is needed to reduce decoding time. In this dissertation, we propose a two-stage multi-threaded manager including application thread manager (ATM) and decoding thread manager (DTM) to perform pipeline and parallel processing. Finally, we propose a two-level parallel processing algorithm (TLPPA) which includes frame-level and CTU-level to finish a real-time SHVC decoder based on multi-cores DSP environment. Experimental results show that the proposed DDPBAA can achieve an average memory saving ratio (MSR) about 40%~50% when using 4K image sequences. The proposed two-stage multi-threaded managers enable a real-time software decoding of 4K@33fps based on DDPBAA on a multicore CPU. Moreover, the proposed TLPPA can realize a real-time hardware decoding of 4K@27fps based on DDPBAA on eight cores DSP.