CMOS Mixed-Voltage Digital I/O Buffer Design with Process, Voltage, Temperature, and Leakage Detectors for Slew Rate Auto-adjustment

107

The main theme of this dissertation is associated with the mixed-voltage CMOS input/output (I/O) buffers for data transmission in a PCB-based system, which considers both the dynamic and static leakage currents encountered in modern nano-scale technologies. Aiming at reduction of the inevitable leakage, two mixed-voltage I/ O buffers using 40 nm and 28 nm processes with a leakage-reduction design is proposed and verified by Monte Carlo simulations. The 40 nm mixed-voltage I/O buffer in Chapter 2 utilizes two process detectors in series to improve the detection for SF and FS process corners. Thus, status signals will be turned off after the data transmission of the output signal is complete. This method saves a considerable amount of power dissipation and it is verified by Monte Carlo analysis to achieve better slew rate (SR) variation: 4.32-5.16 (V/μs). The auto-adjustment of slew rate has been measured to achieve SR variation reduction of 20.8% on silicon. The 28 nm mixed-voltage output buffer in Chapter 3 uses a ring-based oscillator to improve the process detection. The appropriate metal-oxide semiconductor (MOS) length is determined by the trade-off between the leakage and the slew rate. The dual-Vth architecture strategy is inspired by prior works and has been adopted in the output stage. The combination of dual-Vth devices is also verified by Monte Carlo analysis to demonstrate that the proposed design not only increases the efficiency, but also reduces the slew rate variation by 8.8% on silicon.