CMOS current mode A/D converter with improved power efficiency using current mirror memory cells.
2004
Nachschlagewerk
Zugriff:
Chi-Hong, Chan.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.
Includes bibliographical references (leaves 114-117).
in English and Chinese.
p.i
摘要 --- p.iii
Acknowledgements --- p.iv
Table of Contents --- p.vi
List of Figures --- p.x
List of Tables --- p.xiii
Chapter 1. --- Introduction --- p.1
Chapter 1.1. --- System on a Chip (SoC) Design Challenges --- p.1
Chapter 1.2. --- Research Objective --- p.3
Chapter 1.3. --- Thesis Organization --- p.3
Chapter 2. --- Fundamentals of CMOS Current Mode A/D converters --- p.5
Chapter 2.1. --- Overview --- p.5
Chapter 2.2. --- Current Mode Signal Processing --- p.5
Chapter 2.2.1. --- Voltage Mode Circuit Design Technique --- p.5
Chapter 2.2.2. --- Current Mode Circuit Design Technique --- p.6
Chapter 2.2.3. --- First Generation (FG) SI Memory Cell vs. Second Generation (SG) SI Memory Cell --- p.7
Chapter 2.3. --- Ideal Nyquist Rate A/D converters --- p.9
Chapter 2.4. --- Static Performance Parameters --- p.13
Chapter 2.4.1. --- Differential Non-Linearity (DNL) --- p.13
Chapter 2.4.2. --- Integral Non-Linearity (INL) --- p.13
Chapter 2.5. --- Performance Parameters in Frequency Domain --- p.15
Chapter 2.5.1. --- Signal-to-Noise and Distortion Ratio (SNDR) --- p.16
Chapter 2.5.2. --- Effective Number of Bits (ENOB) --- p.16
Chapter 2.5.3. --- Spurious Free Dynamic Range (SFDR) --- p.16
Chapter 3. --- Proposed Current Mirror Memory Cell (CMMC) --- p.18
Chapter 3.1. --- Overview --- p.18
Chapter 3.2. --- Working Principle of CMMC --- p.18
Chapter 3.3. --- CMMC vs. FG SI Cells --- p.20
Chapter 3.4. --- Analog Delay Cell Implementation using the two kinds of memory cells --- p.21
Chapter 3.4.1. --- Delay Cell Implementation by FG Memory Cells --- p.22
Chapter 3.4.2. --- Delay Cell Implementation by CMMC --- p.23
Chapter 3.4.3. --- Simulation Results --- p.24
Chapter 3.5. --- Conclusion --- p.27
Chapter 4. --- Architectural Design of the 12-Bit CMOS A/D Converter --- p.28
Chapter 4.1. --- Overview --- p.28
Chapter 4.2. --- The Floating Analog-to-Digital Converter --- p.28
Chapter 4.3. --- Conversion Algorithm --- p.32
Chapter 4.4. --- Accuracy Considerations Due to Circuit Non-Idealities --- p.34
Chapter 4.4.1. --- Gain Error of Residual Generator --- p.34
Chapter 4.4.2. --- Offset Error of Residual Generator --- p.36
Chapter 4.5. --- Speed Consideration --- p.36
Chapter 4.6. --- Power Consumption vs. No. of Bits per Stage --- p.38
Chapter 4.7. --- Final Architectural Design --- p.40
Chapter 5. --- A/D Converter Implementation using CMMC --- p.41
Chapter 5.1. --- Overview --- p.41
Chapter 5.2. --- Current Sample-and-Hold --- p.41
Chapter 5.2.1. --- Signal Independent CFT Cancellation --- p.43
Chapter 5.2.2. --- Signal Dependent CFT Cancellation --- p.44
Chapter 5.2.3. --- Complete CFT Cancellation --- p.45
Chapter 5.2.4. --- CFT Cancellation by Transmission Gate --- p.45
Chapter 5.2.5. --- CFT Cancellation by Dummy Switches --- p.47
Chapter 5.3. --- Common Mode Feed Forward (CMFF) --- p.48
Chapter 5.4. --- Differential Current Comparator --- p.52
Chapter 5.4.1. --- Regenerative Latch --- p.53
Chapter 5.4.2. --- Pre-amplifier --- p.54
Chapter 5.5. --- Residual Generator --- p.55
Chapter 5.6. --- Thermometer to Binary code Decoder --- p.57
Chapter 6. --- Layout Considerations --- p.59
Chapter 6.1. --- Overview --- p.59
Chapter 6.2. --- Process Introduction --- p.59
Chapter 6.3. --- Common Centroid Layout --- p.60
Chapter 6.4. --- The Design of Power Supply Rails --- p.63
Chapter 6.5. --- Shielding --- p.64
Chapter 6.6. --- Layout of the whole design --- p.65
Chapter 7. --- Simulation Results --- p.67
Chapter 7.1. --- Overview --- p.67
Chapter 7.2. --- Simulation Results of the Current Sample-and-Hold --- p.67
Chapter 7.3. --- Simulation Results of the Differential Current Comparator --- p.70
Chapter 7.4. --- Simulation Results of the overall ADC using One-Stage Simulation Result --- p.71
Chapter 7.5. --- Power Simulation of the Overall 12-Bit ADC --- p.75
Chapter 7.6. --- Summary --- p.78
Chapter 8. --- Measurement Results --- p.79
Chapter 8.1. --- Overview --- p.79
Chapter 8.2. --- PCB Design Consideration --- p.79
Chapter 8.3. --- Measurement Setup --- p.82
Chapter 8.4. --- Measurement Result --- p.84
Chapter 8.4.1. --- Static Parameters --- p.84
Chapter 8.4.2. --- Frequency Domain Measures --- p.85
Chapter 8.5. --- Discussion --- p.90
Chapter 9. --- Conclusion --- p.95
Chapter 9.1. --- Research Methodology of this Project --- p.95
Chapter 9.2. --- Comparison between Voltage Mode and Current Mode Circuit --- p.97
Chapter 9.3. --- Contribution of this Project --- p.98
Chapter A. --- Appendices --- p.99
Chapter A.I. --- Small Signal Analysis on CMMC and FG Memory Cell --- p.99
Chapter A.II. --- The ESD Protection on the ADC --- p.102
Chapter A.III. --- The Histogram Test to determine the DNL and INL of ADC --- p.104
Chapter A.IV. --- Measurement Result of a Commercially Available ADC AD7820 --- p.106
Chapter A.V. --- Pin Assignment of the Current Mode ADC --- p.109
Chapter A.VI. --- Schematics of the Current Mode ADC --- p.111
Chapter A.VII. --- The Chip Micrograph --- p.113
Bibliography --- p.114
| Titel: |
CMOS current mode A/D converter with improved power efficiency using current mirror memory cells.
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|---|---|
| Autor/in / Beteiligte Person: | Chan, Chi-Hong. ; Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Link: | |
| Veröffentlichung: | 2004 |
| Medientyp: | Nachschlagewerk |
| Schlagwort: |
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