A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
2010
Online
Elektronische Ressource
This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.
The original publication is available at www.springerlink.com:Jonas Fritzin and Atila Alvandpour, A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS, 2010, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (64), 3, 241-247.http://dx.doi.org/10.1007/s10470-009-9427-2Copyright: Springer Science Business Mediahttp://www.springerlink.com
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A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
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Veröffentlichung: | 2010 |
Medientyp: | Elektronische Ressource |
DOI: | 10.1007.s10470-009-9427-2 |
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