A Low Noise RC-based Phase Interpolator in 16-nm CMOS
2019
Online
Elektronische Ressource
This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm2.
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A Low Noise RC-based Phase Interpolator in 16-nm CMOS
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Veröffentlichung: | 2019 |
Medientyp: | Elektronische Ressource |
DOI: | 10.1109.TCSII.2018.2823902 |
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