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A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card software driver is used to set up the dual display video controller configurations that assist with the functioning of the digital video compression that is a hardware combination of Run-Length, Huffman encoding and MPEG located on the same monitored user video card. One of the video controller's I2C ports is used to control the compression video circuits and as the pathway for the custom Ethernet communications, thus avoiding an additional costly connection to the user's main computer bus. The first video stream from the dual head video controller chip is used for regular viewing by the local PC (personal computer) user. The second video flow is a frame delayed version of the first video stream used to for comparing current and old frames as the core digital compression image process that results in an Network Ethernet video output. This invention provides a low cost hardware compression for the popular XGA, UXGA VESA computer graphics formats.

Titel:	Network Hardware Graphics Adapter Compression
Autor/in / Beteiligte Person:	McGowan, Scott James
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2008
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20080204465 Publication Date: August 28, 2008 Appl. No: 12/102735 Application Filed: April 14, 2008 Assignees: (Redmond, WA, US) Claim: 1. A novel Network Video Graphics Adapter Compressor Card that reduces cost and improves function for creation of a Network-Ethernet video compressed data stream of a users viewed video, by using the video dual head video controller's two phase locked video stream outputs such that the data stream from the primary scan engine as the current frame, then storing that frame again, with a slight delay, back into the video controller via its zoom video input port, whereas that frame is then read out of memory, one frame time later, via the second head scan engine, as the old frame, thus providing the current and old frames to be compared real-time in the FPGA for the purpose of segregating any changed image pixels, as the core process of video data compression. Claim: 2. That the 32 pixel clock delay is not an exact figure, whereas the delay is long enough to prevent the current frame being stored via the zoom video input port from overwriting the old frame being read out of the same memory location at the same time, at the same memory address block, but no so long of a delay as to incur unnecessary FIFO buffer cost on the final Network Video Graphics Adapter Compressor Card product. Claim: 3. That the on-board general purpose micro processor in the dual head video controller works in conjunction with the FPGA to count vertical syncs to thus create a local software interrupt event to then update the dual head video controller's two scan engines start address registers and the zoom input port write-start address register to thus step though a series of new memory start memory locations in a round-robin fashion to create up to 16 separate image data flows from a Network Video Graphics Adapter Compressor Card. Current U.S. Class: 345/547 Current International Class: 09

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Network Hardware Graphics Adapter Compression