| Sonstiges: |
- Nachgewiesen in: USPTO Patent Applications
- Sprachen: English
- Document Number: 20090265677
- Publication Date: October 22, 2009
- Appl. No: 12/104461
- Application Filed: April 17, 2008
- Claim: 1. A clock generation circuit comprising: a first waveform generator comprising a counter that is clocked by an input clock signal, wherein said counter is adapted to receive a plurality of output clock signal specifications and to generate a pair of first waveform signals based on said output clock signal specifications; and, a deskewer circuit adapted to receive said pair of first waveform signals from said first waveform generator, a pair of second waveform signals from a second waveform generator, and said input clock signal, wherein said deskewer circuit is further adapted to selectively gate said input clock signal with one of said pair of first waveform signals and said pair of second waveform signals in order to generate an output clock signal that is essentially synchronously linked to said input clock signal.
- Claim: 2. The circuit according to claim 1, all the limitations of which are incorporated herein by reference, wherein said output clock signal specifications comprise built-in self-test (BIST) engine supplied output clock signal specifications for BIST operations.
- Claim: 3. The circuit according to claim 1, all the limitations of which are incorporate herein by reference, wherein said output clock signal specifications comprise user supplied output clock signal specifications for one of functional operations and test operations.
- Claim: 4. The circuit according to claim 1, wherein said output clock signal specifications comprise at least one of mode inputs, divide by inputs and width inputs.
- Claim: 5. The circuit according to claim 1, all the limitations of which are incorporate herein by reference, wherein said first waveform generator further comprises a controller in communication with said counter and adapted to control selection by said counter between generation of said pair of first waveform signals based on built-in self test (BIST) engine-supplied output clock signal specifications and generation of said pair of first waveform signals based on user-supplied output clock signal specifications.
- Claim: 6. The circuit according to claim 5, all the limitations of which are incorporate herein by reference, wherein said controller is further adapted to locally start and stop a free-running clock input on demand without delay.
- Claim: 7. The circuit according to claim 1, all the limitations of which are incorporate herein by reference, wherein said first waveform generator further comprises a clock divider capable of dividing said input clock signal based on said output clock signal specifications.
- Claim: 8. The circuit according to claim 1, all the limitations of which are incorporate herein by reference, wherein said first waveform generator further comprises a controller in communication with said deskewer circuit and adapted to control selection by said deskewer circuit of one of said pair of first waveform signals and said pair of second waveform signals for gating with said input clock signal.
- Claim: 9. The circuit according to claim 1, all the limitations of which are incorporated herein by reference, wherein said deskewer circuit allows a same clock path to be used for deskewing both said pair of first waveform signals and said pair of second waveform signals.
- Claim: 10. The circuit according to claim 1, all the limitations of which are incorporated herein by reference, wherein said deskewer circuit comprises: a pair of gates adapted to select one of said pair of first waveform signals and said pair of second waveform signals for processing, wherein each of said gates is adapted to receive one first waveform signal from said first waveform signal generator and one second waveform signal from said second waveform signal generator; and a first set of parallel connected latches, a second set of parallel connected latches and a multiplexer connected in series for selectively gating said input clock signal with said one of said pair of first waveform signals and said pair of second waveform signals selected for processing in order to generate said output clock signal.
- Claim: 11. The circuit according to claim 10, all the limitations of which are incorporated herein by reference, wherein said deskewer circuit further comprises: a second pair of gates connected in series between said second set of parallel connected latches and said multiplexer, wherein said second pair of gates are adapted to allow selective gating of additional input clock signals during generation of said output clock signal.
- Claim: 12. A clock generation method comprising: receiving a pair of first waveform signals from a first waveform generator, a pair of second waveform signals from a second waveform generator, and an input clock signal; and selectively gating said input clock signal with one of said pair of first waveform signals and said pair of second waveform signals in order to generate an output clock signal that is essentially synchronously linked to said input clock signal.
- Claim: 13. The method according to claim 12, all the limitations of which are incorporated herein by reference, further comprising, receiving, by said first waveform generator, output clock signal specifications supplied by a built-in self-test (BIST) engine for BIST operations; and generating, by said first waveform generator, said pair of first waveform signals based on said output clock signal specifications.
- Claim: 14. The method according to claim 13, wherein said output clock signal specifications comprise at least one of mode inputs, divide by inputs and width inputs.
- Claim: 15. The method according to claim 12, all the limitations of which are incorporate herein by reference, further comprising, receiving, by said first waveform generator, output clock signal specifications supplied by a user for one of functional operations and test operations; and generating, by said first waveform generator, said pair of first waveform signals according to said output clock signal specifications.
- Claim: 16. The method according to claim 12, all the limitations of which are incorporate herein by reference, further comprising locally starting and stopping a free-running clock input on demand without delay.
- Claim: 17. The method according to claim 12, all the limitations of which are incorporate herein by reference, wherein said generating of said pair of first waveform signals further comprises: dividing said input clock signal based on a divide by input in said output clock signal specifications.
- Claim: 18. A design structure embodied in a machine readable medium, said design structure comprising a clock generation circuit comprising: a first waveform generator comprising a counter that is clocked by an input clock signal, wherein said counter is adapted to receive a plurality of output clock signal specifications and to generate a pair of first waveform signals based on said output clock signal specifications; and, a deskewer circuit adapted to receive said pair of first waveform signals from said first waveform generator, a pair of second waveform signals from a second waveform generator, and said input clock signal, wherein said deskewer circuit is further adapted to selectively gate said input clock signal with one of said pair of first waveform signals and said pair of second waveform signals in order to generate an output clock signal that is essentially synchronously linked to said input clock signal.
- Claim: 19. The design structure according to claim 18, all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist.
- Claim: 20. The design structure of claim 18, wherein said design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
- Current U.S. Class: 716/12
- Current International Class: 03; 06; 06
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