Einzeltreffer — DigiBib

In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks.

Titel:	DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2013
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20130149829 Publication Date: June 13, 2013 Appl. No: 13/689433 Application Filed: November 29, 2012 Assignees: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX, US) Claim: 1. A method of forming a portion of an integrated circuit comprising: forming first and second source/drain regions in active areas of an NMOS region by implanting a first dose of phosphorous, a first dose of arsenic and a first dose of nitrogen; performing a first process thermal process that activates the formed first and second source/drain regions in the NMOS region; implanting the first source/drain region and a third source/drain region with a second dose of phosphorus. Claim: 2. The method of claim 1 wherein the second dose of phosphorous is equal to or larger than the first dose of phosphorous. Claim: 3. The method of claim 1, further comprising forming well regions and isolation regions in a semiconductor substrate of the NMOS region prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 4. The method of claim 3, further comprising forming gate electrodes in the NMOS region prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 5. The method of claim 4, further comprising forming first source/drain sidewall spacers prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 6. The method of claim 5, further comprising performing an LDD implantation in the source/drain regions prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 7. The method of claim 6, further comprising performing a thermal anneal prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 8. The method of claim 7, further comprising forming second source/drain sidewall spacers prior to implanting the first dose of phosphorous and a first dose of arsenic. Claim: 9. The method of claim 1, further comprising depositing a layer of tensile material on the NMOS region subsequent to implanting the source/drain regions with a second dose of phosphorus. Claim: 10. The method of claim 1, further comprising performing an ultra high temperature anneal process wherein the ultra high temperature anneal process is performed above 1200 C for less than 100 milliseconds after forming first and second source/drain regions in active areas of the NMOS region. Claim: 11. The method of claim 1, further comprising a second thermal process wherein the second thermal process is a spike anneal performed at a temperature within the range of about 900-1100 degrees Celsius after forming first and second source/drain regions in active areas of the NMOS region. Claim: 12. The method of claim 1, further comprising performing an ultra high temperature anneal process wherein the ultra high temperature anneal process is performed above 1200 C for less than 100 milliseconds and a second thermal process wherein the second thermal process is a spike anneal performed at a temperature within the range of about 900-1100 degrees Celsius after forming first and second source/drain regions in active areas of the NMOS region. Claim: 13. The method of claim 1, further comprising performing an ultra high temperature anneal process wherein the ultra high temperature anneal process is performed above 1200 C for less than 100 milliseconds after implanting the first source/drain region and a third source/drain region with a second dose of phosphorus. Claim: 14. The method of claim 1, further comprising a second thermal process wherein the second thermal process is a spike anneal performed at a temperature within the range of about 900-1000 degrees Celsius after implanting the first source/drain region and a third source/drain region with a second dose of phosphorus. Claim: 15. The method of claim 1, further comprising performing an ultra high temperature anneal process wherein the ultra high temperature anneal process is performed above 1200 C for less than 100 milliseconds and a second thermal process wherein the second thermal process is a spike anneal performed at a temperature within the range of about 900-1000 degrees Celsius after implanting the first source/drain region and a third source/drain region with a second dose of phosphorus. Claim: 16. The method of claim 1 wherein a first type of NMOS transistors are formed by the first source/drain regions and a first group of gate electrodes, wherein a second type of NMOS transistors are formed by the second source/drain regions and a second group of gate electrodes and wherein a third type of NMOS transistors are formed by the third source/drain regions and a third group of gate electrodes. Claim: 17. The method of claim 1 wherein NMOS transistors are formed by the first, second and third source/drain regions and a group of gate electrodes; wherein the gate electrodes and gate dielectric material are removed and replaced with metal gates and high K (dielectric) material. Claim: 18. The method of claim 16 wherein the first, second and third NMOS transistors are tri-gate field-effect transistors. Claim: 19. The method of claim 16 wherein the first, second and third NMOS transistors are FINFETs. Claim: 20. The method of claim 1 wherein dopants selected from the group consisting of germanium, and carbon are implanted after implanting a first dose of phosphorous, a first dose of arsenic and a first dose of nitrogen. Claim: 21. The method of claim 1 further comprising implanting Germanium and/or Arsenic and/or Carbon and/or Nitrogen when implanting the source/drain regions with a second dose of phosphorus. Claim: 22. The method of claim 1 wherein the first thermal process is a spike anneal performed at a temperature within the range of about 900-1050 degrees Celsius. Claim: 23. A method of forming a portion of an integrated circuit comprising: implanting a first dose of phosphorous, a first dose of arsenic and a first dose of nitrogen into a first poly silicon block and a second poly silicon block; performing a first process thermal process that activates the first dose of phosphorous, the first dose of arsenic and the first dose of nitrogen; implanting a second dose of phosphorus into a third poly silicon block and the first poly silicon block. Claim: 24. The method of claim 23 wherein the second dose of phosphorous is equal to or larger than the first dose of phosphorous. Claim: 25. The method of claim 23 wherein a first type of n-type resistor is formed by the first poly silicon block, wherein a second type of n-type resistor is formed by the second poly silicon block and a third type of n-type resistor is formed by the third poly silicon block. Claim: 26. The method of claim 23 wherein a first type of capacitor is formed by the first poly silicon block, wherein a second type of capacitor is formed by the second poly silicon block and a third type of capacitor is formed by the third poly silicon block. Claim: 27. A method of forming a portion of an integrated circuit comprising: forming well regions and isolation regions in a semiconductor substrate of an NMOS region; forming gate electrodes in the NMOS region; forming first source/drain sidewall spacers; forming lightly-doped source/drain regions in active areas of the NMOS region; performing a thermal anneal; forming second source/drain sidewall spacers; forming source/drain regions in active areas of the NMOS region by implanting a first dose of phosphorous, a first dose of arsenic and a first dose of nitrogen; performing a first thermal process that activates the formed source/drain regions in the NMOS region; implanting the source/drain regions with a second dose of phosphorus; depositing a layer of tensile material on the NMOS region; performing a second thermal process; and removing the layer of tensile material. Claim: 28. The method of claim 27 further comprising implanting one or more doses of carbon and/or germanium with the said first and/or the second source drain implants. Current U.S. Class: 438/294 Current International Class: 01

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DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR