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METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)

2018
Online Patent
Zugriff:
View record in USPTO Patent Applications (Volltext)

Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Titel:
METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)
Link:
Veröffentlichung: 2018
Medientyp: Patent
Sonstiges:
  • Nachgewiesen in: USPTO Patent Applications
  • Sprachen: English
  • Document Number: 20180083036
  • Publication Date: March 22, 2018
  • Appl. No: 15/613712
  • Application Filed: June 05, 2017
  • Assignees: Samsung Eletronics Co., Ltd. (Suwon-si, KR)
  • Claim: 1. A method of fabricating a Fin Field Effect Transistor (FinFet) structure using Local Layout Effects (LLE), the method comprising: removing one or more fingers of an active P-type FinFet (PFET) gate of some PFET gates from a standard FinFET cell; introducing a Half-Double Diffusion Break (Half-DDB) on an N-type FinFET (NFET) side of a cell boundary using a cut-poly layer to isolate the some PFET gates and some NFET gates; and converting the removed one or more fingers of the active PFET gate to at least two floating PFET gates by shorting a drain terminal and a source terminal of the active PFET gate to a common net.
  • Claim: 2. The method of claim 1, wherein converting e removed one or more fingers of the active PFET gate includes: converting the removed one or more PFET fingers of the active PFET gate to at least two floating PFET gates by shorting the drain terminal and the source terminal of the active PFET gate to one of a common internal net and a common power net.
  • Claim: 3. The method of claim 1, further comprising: removing one or more fins from the NFET side of the cell boundary.
  • Claim: 4. The method of claim 1, further comprising: removing one or more PFET fins along with one or more PFET fingers; and converting the removed one or more PFET fingers of the active PFET gate to at least two floating PFET gates by shorting the drain terminal and the source terminal of the active PFET gate to one of a common power net and a common internal net.
  • Claim: 5. The method of claim 1, further comprising: removing one or more NFET fins from the NFET side of the cell boundary; and retaining the some of the PFET gates in active state.
  • Claim: 6. The method of claim 1, further comprising: removing one or more PFET fins while retaining some of the PFET gates in active state.
  • Claim: 7. The method of claim 1, further comprising: converting at least one of the some PFET gates cut from the some NFET gates to a floating gate, where the drain terminal and source terminal of the floating gate is connected to one of a common power net and common internal net, where another at least one of the some PFET gates is converted to an inactive gate using a Single Diffusion Break on the PFET gate cut from the NFET gate.
  • Claim: 8. The method of claim 7, wherein, when viewed from a plan view, a position of the at least one floating gate is one of to a left of the Single Diffusion Break and to a right of the Single Diffusion Break.
  • Claim: 9. The method of claim 1, further comprising: converting at least one DDB of a standard FinFet cell to a half-DDB on the NFET side inside the cell boundary using a cut poly layer to isolate the PFET gates and the NFET gates.
  • Claim: 10. The method of claim 1, further comprising: introducing a hybrid DUB structure on the standard FinFet cell; and removing one or more NFET fins belonging to one or more inputs.
  • Claim: 11. The method of claim 1, further comprising: inserting the Half-DDB on an N-type FinFet (NFET) side of the cell boundary using the cut-poly layer to isolate the PFET and NFET gates; and removing one or more NFET fins belonging to an input directly connected to an outside.
  • Claim: 12. The method of claim 1, further comprising: converting at east one of existing Double Diffusion Breaks (DDB) to a Half-DDB on the NFET side inside the FinFet cell using the cut-poly layer to isolate the PFET gates and the NFET gates; and adding one or more PFET gate active fingers in a space created after removal of the DDB.
  • Claim: 13. The method of claim 12, further comprising: removing one or more PFET fins for each transistor in the FinFet cell.
  • Claim: 14. The method of claim 1, further comprising: converting at least one of some Double Diffusion Break to a Half-DDB on the NFET side inside the FinFet cell using the cut-poly layer to isolate the some PFET gates and the some NFET gates; and creating at least two new PFET gates in a space created; and converting at least one of the two new HET gates into a Single Diffusion Break (SUB) and at least another of the two new PFET gates to a floating gate by connecting drain and source terminals to one of a common power net and a common internal net.
  • Claim: 15. The method of claim 14, wherein, when viewed from a plan view, a position of the at least one floating gate is one of to a left of the Single Diffusion Break and to a right of the Single Diffusion Break.
  • Claim: 16. A method of manufacturing a semiconductor device, comprising: designing a poly reticle using a standard FinFET cell and removing one or more fingers of a standard cell of the poly reticle; converting the removed one or more fingers of the poly reticle by shorting a drain terminal and a source terminal to a common net; designing a cut-poly reticle with a half-double diffusion break isolate PITT gates and NFET gates in the standard cell; and using the poly reticle and the cut-poly reticle as photomasks to manufacture the semiconductor device.
  • Claim: 17. The method of claim 16, further comprising: designing a fin reticle; removing one or more NFET fins in the fin reticle, the one or more NFET fins directly connected to an input, the one or more fins included in the standard cell; and using the fin reticle as a photomask to manufacture the semiconductor device.
  • Claim: 18. The method of claim 17, further comprising: designing a metal reticle connecting the drain terminal and the source terminal; and using the eta reticle as a photomask to manufacture the semiconductor device.
  • Current International Class: 01

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