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Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Titel:	METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2019
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20190006388 Publication Date: January 3, 2019 Appl. No: 16/124946 Application Filed: September 07, 2018 Assignees: Samsung Electronics Co., Ltd. (Suwon-si, KR) Claim: 1. A fin field effect transistor (FinFet) structure comprising: a half double diffusion break (Half-DBB); a first transistor; and a cutting layer configured to isolate the Half-DBB and the first transistor; wherein the first transistor is floated by shorting a drain terminal and a source terminal of the first transistor to a common power net. Claim: 2. The FinFet structure of claim 1, further comprising a second transistor; and wherein the second transistor is floated by shorting a drain terminal and a source terminal of the second transistor to the common power net. Claim: 3. The FinFet structure of claim 2, wherein the second transistor is located right next to the first transistor. Claim: 4. The FinFet structure of claim 3, wherein the cutting layer is configured to isolate the Half-DBB and second transistor. Claim: 5. The FinFet structure of claim 4, wherein the FinFet structure is a standard FinFet cell. Claim: 6. The FinFet structure of claim 5, wherein the second transistor and the Half-DBB are disposed inside a cell boundary of the standard FinFet cell. Claim: 7. The FinFet structure of claim 5, wherein the Half-DBB is on a N-type FinFet side and the first transistor is on a P-type FinFet side, wherein the N-type FinFet side includes N number of fins and the P-type FinFet side includes M number of fins, wherein the N is different from the M, and wherein the N and M are integer. Claim: 8. The FinFet structure of claim 7, wherein the N is greater than the M. Claim: 9. The FinFet structure of claim 7, wherein the second transistor is located right next to the first transistor. Claim: 10. A fin field effect transistor (FinFet) structure comprising: a half double diffusion break (Half-DBB) on a first side of the FinFet structure; a first transistor on a second side of the FinFet structure; and a cutting layer configured to isolate the Half-DBB and the first transistor; wherein a gate of the first transistor is inactive using a single diffusion break(SDB). Claim: 11. The FinFet structure of claim 10, wherein the first side side includes N number of fins and the second side includes M number of fins, wherein the N is different from the M, and wherein the N and M are integer. Claim: 12. The FinFet structure of claim 11, wherein the N is greater than the M. Claim: 13. The FinFet structure of claim 10, further comprising a second transistor; and wherein the second transistor is floated by shorting a drain terminal and a source terminal of the second transistor to the common power net. Claim: 14. The FinFet structure of claim 13, wherein the cutting layer is configured to isolate the Half-DBB and second transistor. Claim: 15. The FinFet structure of claim 14, wherein the second transistor and the Half-DBB are disposed inside a cell boundary of the standard FinFet cell. Claim: 16. The FinFet structure of claim 15, wherein the second transistor is located right next to the first transistor. Claim: 17. The FinFet structure of claim 16, wherein the first side is a N-type FinFet side and the second side is a P-type FinFet side. Claim: 18. The FinFet structure of claim 13, wherein the second transistor is located right next to the first transistor. Current International Class: 01

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METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)