Einzeltreffer — DigiBib

A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.

Titel:	SEMICONDUCTOR DEVICE HAVING OVERLAY PATTERN
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2019
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20190155174 Publication Date: May 23, 2019 Appl. No: 16/196626 Application Filed: November 20, 2018 Claim: 1. A semiconductor device, comprising: a semiconductor substrate comprising an in-cell area and a scribe lane defining the in-cell area; a first overlay pattern on the semiconductor substrate; and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern, and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern. Claim: 2. The semiconductor device as claimed in claim 1, wherein a dummy pattern is around the first overlay pattern and the second overlay pattern is between the first overlay pattern and the dummy pattern. Claim: 3. The semiconductor device as claimed in claim 2, wherein the second overlay pattern surrounds the first overlay pattern. Claim: 4. The semiconductor device as claimed in claim 2, wherein a shortest distance between an edge of the first overlay pattern and the dummy pattern is at least about 2 micrometers, and a shortest distance between the edge of the first overlay pattern and the second overlay pattern is about 0.5 micrometer to about 1.5 micrometer. Claim: 5. The semiconductor device as claimed in claim 1, wherein the first overlay pattern comprises only a first line-and-space pattern extending in a first direction. Claim: 6. The semiconductor device as claimed in claim 1, wherein the first overlay pattern comprises a first line-and-space pattern extending in a first direction and a second line-and-space pattern extending in a second direction perpendicular to the first direction. Claim: 7. The semiconductor device as claimed in claim 1, wherein the second overlay pattern comprises a first sub-pattern and a second sub-pattern respectively corresponding to a first cell pattern group and a second cell pattern group located in the in-cell area, the first cell pattern group and the second cell pattern group being at the same level. Claim: 8. The semiconductor device as claimed in claim 7, wherein: the second overlay pattern further comprises a third sub-pattern corresponding to the first cell pattern group located in the in-cell area at the same level, and a direction in which the first sub-pattern and the second sub-pattern are arranged is different from a direction in which the second sub-pattern and the third sub-pattern are arranged. Claim: 9. The semiconductor device as claimed in claim 1, wherein the second overlay pattern comprises a first sub-pattern and a fourth sub-pattern respectively corresponding to a first cell pattern group and a third cell pattern group located in the in-cell area, the first cell pattern group and the third cell pattern group being at a different level. Claim: 10. The semiconductor device as claimed in claim 1, wherein: the first overlay pattern and the second overlay pattern form one overlay pattern group, and the overlay pattern group is in the scribe lane. Claim: 11. The semiconductor device as claimed in claim 1, wherein: the first overlay pattern and the second overlay pattern form one overlay pattern group, and the overlay pattern group is in the in-cell area. Claim: 12. A semiconductor device, comprising: a semiconductor substrate; a first overlay pattern on the semiconductor substrate, the first overlay pattern comprising line-and-space patterns each extending in a first direction and a second direction perpendicular to the first direction; and a second overlay pattern on the semiconductor substrate, the second overlay pattern surrounding the first overlay pattern within a forbidden region surrounding the first overlay pattern. Claim: 13. The semiconductor device as claimed in claim 12, wherein the second overlay pattern is dependent on an orientation of a lithographic illumination system used to manufacture the semiconductor device. Claim: 14. The semiconductor device as claimed in claim 13, wherein the second overlay pattern comprises only a line-and-space pattern extending in a same direction. Claim: 15. A semiconductor device, comprising: a semiconductor substrate comprising an in-cell area and a scribe lane defining the in-cell area; a first overlay pattern on the semiconductor substrate; and a second overlay pattern adjacent to the first overlay pattern, the second overlay pattern being in a forbidden region of the first overlay pattern. Claim: 16. The semiconductor device as claimed in claim 15, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern. Claim: 17. The semiconductor device as claimed in claim 16, wherein the second overlay pattern is a scanning electron microscope (SEM) overlay pattern. Claim: 18. The semiconductor device as claimed in claim 17, wherein: the second overlay pattern comprises a first sub-pattern and a second sub-pattern corresponding to a first cell pattern group and a second cell pattern group, respectively, located in the in-cell area, and the first cell pattern group and the second cell pattern group are located at a first level. Claim: 19. The semiconductor device as claimed in claim 18, wherein the second overlay pattern further comprises a fourth sub-pattern corresponding to a third cell pattern group located in the in-cell area, the fourth sub-pattern being located at a second level different from the first level. Claim: 20. The semiconductor device as claimed in claim 19, wherein: the second level is higher than the first level, and the first sub-pattern and the second sub-pattern are covered with an interlayer insulating layer so that images of the first sub-pattern and the second sub-pattern are extractable by SEM. Current International Class: 03; 06; 01; 01; 01; 01

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SEMICONDUCTOR DEVICE HAVING OVERLAY PATTERN