| Sonstiges: |
- Nachgewiesen in: USPTO Patent Applications
- Sprachen: English
- Document Number: 20200313681
- Publication Date: October 1, 2020
- Appl. No: 16/366122
- Application Filed: March 27, 2019
- Claim: 1. An oscillator circuit, comprising: a digitally controlled oscillator (DCO) circuit, comprising: a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword, wherein the input tuning codeword comprises a set of integer bits and a set of fractional bits, and wherein the tuning circuit comprises: an integer tuning circuit configured to process the integer tuning codeword based on switching a plurality of integer tuning capacitors associated therewith, in order to implement the input tuning codeword, wherein the integer tuning codeword comprises an integer tuning range associated therewith; and a fractional tuning circuit configured to process the fractional tuning codeword based on switching a plurality of fractional tuning capacitors associated therewith, in order to implement the input tuning word, wherein the fractional tuning codeword comprises a fractional tuning range associated therewith; wherein the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.
- Claim: 2. The oscillator circuit of claim 1, wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword, and wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword and a redundant integer bit, wherein the redundant integer bit is redundant to a bit associated with the integer tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 3. The oscillator circuit of claim 2, wherein the redundant integer bit comprises a most significant bit (MSB) of the fractional tuning codeword and wherein the MSB of fractional tuning codeword is redundant to a least significant bit (LSB) of the integer tuning codeword.
- Claim: 4. The oscillator circuit of claim 2, wherein the redundant integer bit comprises two or more redundant integer bits, wherein the two or more redundant integer bits are redundant to two or more bits associated with the integer tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Claim: 5. The oscillator circuit of claim 1, wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword, and wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword and a redundant fractional bit, wherein the redundant fractional bit is redundant to a bit associated with the fractional tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 6. The oscillator circuit of claim 5, wherein the redundant fractional bit comprises a least significant bit (LSB) of the integer tuning codeword and wherein the LSB of the integer tuning codeword is redundant to a most significant bit (MSB) of the fractional tuning codeword.
- Claim: 7. The oscillator circuit of claim 5, wherein the redundant fractional bit comprises two or more redundant integer bits, wherein the two or more redundant fractional bits are redundant to two or more bits associated with the fractional tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Claim: 8. The oscillator circuit of claim 1, further comprising a hysteresis logic circuit configured to split the input tuning codeword to form the integer tuning codeword and the fractional tuning codeword.
- Claim: 9. The oscillator circuit of claim 8, wherein the hysteresis logic circuit is configured to split the input tuning codeword, based on a change direction of the input tuning codeword.
- Claim: 10. The oscillator circuit of claim 9, wherein the hysteresis logic circuit is configured to split the input tuning codeword into a first integer tuning codeword and a corresponding first fractional tuning codeword, for increasing input tuning codeword, and wherein the hysteresis logic circuit is configured to split the input tuning codeword into a second, different, integer tuning codeword and a corresponding second fractional tuning codeword, for decreasing input tuning codeword.
- Claim: 11. The oscillator circuit of claim 1, wherein the fractional tuning circuit is configured to process the fractional tuning codeword based on processing an oversampled integer codeword derived based on the fractional tuning codeword.
- Claim: 12. The oscillator circuit of claim 11, further comprising a modulation circuit configured to convert the fractional tuning codeword into the oversampled integer codeword.
- Claim: 13. A digitally controlled oscillator (DCO) circuit, comprising: a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword, wherein the input tuning codeword comprises a set of integer bits and a set of fractional bits, and wherein the tuning circuit comprises: an integer tuning circuit configured to process the integer tuning codeword based on switching a plurality of integer tuning capacitors associated therewith, in order to implement the input tuning codeword, wherein the integer tuning codeword comprises an integer tuning range associated therewith; and a fractional tuning circuit configured to process the fractional tuning codeword based on switching a plurality of fractional tuning capacitors associated therewith, in order to implement the input tuning word, wherein the fractional tuning codeword comprises a fractional tuning range associated therewith; wherein the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.
- Claim: 14. The DCO circuit of claim 13, wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword, and wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword and a redundant integer bit, wherein the redundant integer bit is redundant to a bit associated with the integer tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 15. The DCO circuit of claim 14, wherein the redundant integer bit comprises a most significant bit (MSB) of the fractional tuning codeword and wherein the MSB of fractional tuning codeword is redundant to a least significant bit (LSB) of the integer tuning codeword.
- Claim: 16. The DCO circuit of claim 14, wherein the redundant integer bit comprises two or more redundant integer bits, wherein the two or more redundant integer bits are redundant to two or more bits associated with the integer tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Claim: 17. The DCO circuit of claim 13, wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword, and wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword and a redundant fractional bit, wherein the redundant fractional bit is redundant to a bit associated with the fractional tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 18. The DCO circuit of claim 17, wherein the redundant fractional bit comprises a least significant bit (LSB) of the integer tuning codeword and wherein the LSB of the integer tuning codeword is redundant to a most significant bit (MSB) of the fractional tuning codeword.
- Claim: 19. The DCO circuit of claim 17, wherein the redundant fractional bit comprises two or more redundant integer bits, wherein the two or more redundant fractional bits are redundant to two or more bits associated with the fractional tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Claim: 20. The DCO circuit of claim 13, wherein the fractional tuning circuit is configured to process the fractional tuning codeword based on processing an oversampled integer codeword derived based on the fractional tuning codeword.
- Claim: 21. A method for tuning an oscillation frequency of a digitally controlled oscillator (DCO) circuit, comprising: processing an integer tuning codeword associated with an input tuning codeword at an integer tuning circuit comprising a plurality of integer tuning capacitors, based on switching the plurality of integer tuning capacitors, in order to implement the input tuning codeword, wherein the integer tuning codeword comprises an integer tuning range associated therewith; and processing a fractional tuning codeword associated with the input tuning codeword at a fractional tuning circuit comprising a plurality of fractional tuning capacitors, associated with the DCO circuit, based on switching the plurality of fractional tuning capacitors, in order to implement the input tuning codeword, wherein the fractional tuning codeword comprises a fractional tuning range associated therewith; wherein the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.
- Claim: 22. The method of claim 21, further comprising splitting the input tuning codeword to form the integer tuning codeword and the fractional tuning codeword, at a hysteresis logic circuit, based on a change direction of the input tuning codeword.
- Claim: 23. The method of claim 21, wherein processing the fractional tuning codeword, at the fractional tuning circuit, comprises processing an oversampled integer codeword derived based on the fractional tuning codeword.
- Claim: 24. The method of claim 21, wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword, and wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword and a redundant integer bit, wherein the redundant integer bit is redundant to a bit associated with the integer tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 25. The method of claim 24, wherein the redundant integer bit comprises a most significant bit (MSB) of the fractional tuning codeword and wherein the MSB of fractional tuning codeword is redundant to a least significant bit (LSB) of the integer tuning codeword.
- Claim: 26. The method of claim 24, wherein the redundant integer bit comprises two or more redundant integer bits, wherein the two or more redundant integer bits are redundant to two or more bits associated with the integer tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Claim: 27. The method of claim 21, wherein the fractional tuning codeword comprises a set of fractional bits corresponding to the set of fractional bits associated with the input tuning codeword, and wherein the integer tuning codeword comprises a set of integer bits corresponding to the set of integer bits associated with the input tuning codeword and a redundant fractional bit, wherein the redundant fractional bit is redundant to a bit associated with the fractional tuning codeword, in order to enable the fractional tuning range to cover two steps of the integer tuning range.
- Claim: 28. The method of claim 27, wherein the redundant fractional bit comprises a least significant bit (LSB) of the integer tuning codeword and wherein the LSB of the integer tuning codeword is redundant to a most significant bit (MSB) of the fractional tuning codeword.
- Claim: 29. The method of claim 27, wherein the redundant fractional bit comprises two or more redundant integer bits, wherein the two or more redundant fractional bits are redundant to two or more bits associated with the fractional tuning word, respectively, in order to enable the fractional tuning range to cover more than two steps of the integer tuning range.
- Current International Class: 03
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