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The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.

Titel:	MANUFACTURING METHOD FOR CMOS LTPS TFT SUBSTRATE
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2021
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20210091124 Publication Date: March 25, 2021 Appl. No: 16/309446 Application Filed: September 18, 2018 Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd. (Wuhan, CN) Claim: 1. A manufacturing method for a complementary metal oxide semiconductor (CMOS) low temperature poly-silicon (LTPS) thin film transistor (TFT) substrate, comprising S1: providing a substrate, and forming a buffer layer on the substrate, a first poly-silicon (poly-Si) active layer and a second poly-Si active layer separated apart on the buffer layer, a gate insulation layer covering the first and second poly-Si active layers, a metallic layer deposited on the gate insulation layer, and a first photoresist pattern above a middle section of the first poly-Si active layer and a second photoresist pattern entirely covering the second poly-Si active layer on the metallic layer by coating photoresist on the metallic layer and conducting exposure and development to the photoresist with a semi-transparent mask, where the second photoresist pattern comprises a first photoresist section in the middle and a second photoresist section adjoining lateral sides of the first photoresist section and having a thickness smaller than the first photoresist section; S2: forming a first quasi-gate electrode above the middle section of the first poly-Si active layer and a second quasi-gate electrode entirely covering the second poly-Si active layer by conducting a first etching to the metallic layer using the first and second photoresist patterns as shielding layer; S3: obtaining a first source/drain contact region at lateral end sections of the first poly-Si active layer by conducting N-type ion heavy doping to lateral end sections of the first poly-Si active layer not covered by the first quasi-gate electrode using the first photoresist pattern as shielding layer; S4: reducing thickness of the first photoresist pattern and the second photoresist pattern by conducting ashing process to the first and second photoresist patterns, so that the thickness of the first photoresist pattern and the first photoresist section of the second photoresist pattern is reduced, and the second photoresist section of the second photoresist pattern is removed to expose two lateral ends of the second poly-Si active layer; S5: obtaining a first gate electrode from the first quasi-gate electrode and a second gate electrode from the second quasi-gate electrode by conducting a second etching to the metallic layer and lifting the remaining first and second photoresist patterns, where width of the second quasi-gate electrode is reduced as its lateral ends are etched, and the second gate electrode is above the middle section of the second poly-Si active layer; S6: obtaining a first ditch region in the middle section of the first poly-Si active layer below the first gate electrode, and a first lightly doped drain (LDD) region between the first ditch region and the first source/drain contact region by conducting N-type ion light doping to the first poly-Si active layer using the first gate electrode as shielding layer; and S7: forming a photoresist protection layer on the gate insulation layer and the first gate electrode that entirely covers the first poly-Si active layer, obtaining a second source/drain contact region at lateral end sections of the second poly-Si active layer and a second ditch region in the middle section of the second poly-Si active layer below the second gate electrode by conducting P-type ion heavy doping to lateral end sections of the second poly-Si active layer not covered by the second gate electrode using the second gate electrode as shielding layer, and removing the photoresist protection layer. Claim: 2. The manufacturing method according to claim 1, wherein the semi-transparent mask of step S1 has an opaque section, a semi-transparent section, and a remaining transparent section; the opaque section is for forming the first photoresist pattern and the first photoresist section of the second photoresist pattern; and the semi-transparent section is for forming the second photoresist section of the second photoresist pattern. Claim: 3. The manufacturing method according to claim 1, wherein the semi-transparent mask of step S1 is a gray tone mask (GTM) or a half tone mask (HTM). Claim: 4. The manufacturing method according to claim 1, wherein the ashing process of step S4 is conducted using oxygen. Claim: 5. The manufacturing method according to claim 1, wherein the second etching of step S5 is a dry etching with an etching gas comprising oxygen and chlorine. Claim: 6. The manufacturing method according to claim 1, wherein the first etching of step S2 is a dry etching with an etching gas comprising one or more of sulphur hexafluoride (SF6), pentafluoroethane (C2HF5), and carbon tetrafluoride (CF4). Claim: 7. The manufacturing method according to claim 1, wherein the N-type ion heavy doping of step S3 is by phosphorus (P) ions and doping density is 1×1014−1×1015 ions/cm2. Claim: 8. The manufacturing method according to claim 1, wherein the N-type ion light doping of step S6 is by phosphorus (P) ions and doping density is 1×1012−1×1013 ions/cm2. Claim: 9. The manufacturing method according to claim 1, wherein the P-type ion heavy doping of step S7 is by boron (B) ions and doping density is 1×1014−1×1015 ions/cm2. Claim: 10. The manufacturing method according to claim 1, wherein step S1 further comprises, before forming the buffer layer, forming a first shading block and a second shading block laterally spaced apart on the substrate, respectively below the first and second poly-Si active layers. Current International Class: 01; 01

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MANUFACTURING METHOD FOR CMOS LTPS TFT SUBSTRATE