Einzeltreffer — DigiBib

A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block Aj (j=2 to N, where N is an integer) down-converts an analog input signal Sx using a cutoff frequency fj-1 of a channel CHj-1 and A/D-converts an analog signal Saj acquired as a result. A digital processing block Bj doubles the signal strength of a first digital signal S1j acquired by Aj, subtracts a third digital signal S3j-1 of the channel CHj-1 from a second digital signal S2j acquired as a result, up-converts the acquired third digital signal S3j using the cutoff frequency fj-1, and outputs the result to an adder as a channel output signal Syj of a corresponding channel CHj.

Titel:	Analog/Digital Converter
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2021
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20210320667 Publication Date: October 14, 2021 Appl. No: 17/272886 Application Filed: August 21, 2019 Claim: 1.-2. (canceled) Claim: 3. An analog-to-digital converter comprising: N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of channels CHi, wherein i=1 to N and N is an integer, the channels CHi being acquired by dividing a frequency band corresponding to an analog input signal Sx into N parts, the N analog processing blocks Ai being configured to process analog signals of the channels CHi; N digital processing blocks Bi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi, the N digital processing blocks Bi being configured to process digital signals of the channels CHi; and an adder configured to output a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis; wherein each analog processing block Aj of the N analog processing blocks Ai includes: a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1; and a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter; wherein j=2 to N; wherein each digital processing block Bj of the N digital processing blocks Bi includes: a multiplier configured to double a signal strength of a first digital signal S1j acquired by the sub A/D converter of the analog processing block Aj; a subtractor configured to: subtract a third digital signal S3j-1 relating to the channel CHj-1 from a second digital signal S2j acquired by the multiplier; and output a third digital signal S3j of a corresponding channel CHj; and a frequency converter configured to up-convert the third digital signal S3j to obtain an up-converted third digital signal S3j and outputs the up-converted third digital signal S3j to the adder as a channel output signal Syj of the corresponding channel CHj; wherein an analog processing block A1 of the N analog processing blocks Ai includes a sub A/D converter configured to A/D-convert the analog input signal Sx; and wherein a digital processing block B1 of the N digital processing blocks Bi outputs a first digital signal S11 acquired by the sub A/D converter of the analog processing block A1 as a third digital signal of a corresponding channel CH1 and also outputs the first digital signal S11 to the adder as a channel output signal Sy1 of the corresponding channel CH1. Claim: 4. The analog-to-digital converter according to claim 3, wherein the N digital processing blocks Bi each include a digital filter configured to compensate for a frequency characteristic in a corresponding partial band Wi in a band of a first output signal Si1 from an analog processing block Ai of the respective one of the channels CHi based on an inverse transfer function of a signal path through the analog processing block Ai. Claim: 5. An analog-to-digital converter comprising: N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of channels CHi, wherein i=1 to N and N is an integer, the channels CHi being acquired by dividing a frequency band corresponding to an analog input signal Sx into N parts, the N analog processing blocks Ai being configured to process analog signals of the channels CHi, wherein each analog processing block Aj of the N analog processing blocks Ai includes: a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1; and a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter, wherein j=2 to N; N digital processing blocks Bi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi, the N digital processing blocks Bi being configured to process digital signals of the channels CHi; and an adder configured to output a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis. Claim: 6. An analog-to-digital converter according to claim 5, wherein each digital processing block Bj of the N digital processing blocks Bi includes: a multiplier configured to double a signal strength of a first digital signal S1j acquired by the sub A/D converter of the analog processing block Aj; a subtractor configured to: subtract a third digital signal S3j-1 relating to the channel CHj-1 from a second digital signal S2j acquired by the multiplier; and output a third digital signal S3j of a corresponding channel CHj; and a frequency converter configured to up-convert the third digital signal S3j to obtain an up-converted third digital signal S3j and outputs the up-converted third digital signal S3j to the adder as a channel output signal Syj of the corresponding channel CHj. Claim: 7. An analog-to-digital converter according to claim 6, wherein an analog processing block A1 of the N analog processing blocks Ai includes a sub A/D converter configured to A/D-convert the analog input signal Sx. Claim: 8. An analog-to-digital converter according to claim 7, wherein a digital processing block B1 of the N digital processing blocks Bi outputs a first digital signal S11 acquired by the sub A/D converter of the analog processing block A1 as a third digital signal of a corresponding channel CH1 and also outputs the first digital signal S11 to the adder as a channel output signal Sy1 of the corresponding channel CH1. Claim: 9. The analog-to-digital converter according to claim 5, wherein the N digital processing blocks Bi each include a digital filter configured to compensate for a frequency characteristic in a corresponding partial band Wi in a band of a first output signal Si1 from an analog processing block Ai of the respective one of the channels CHi based on an inverse transfer function of a signal path through the analog processing block Ai. Claim: 10. A method of operating an analog-to-digital converter, wherein the method comprises: acquiring, by the analog-to-digital converter, channels CHi by dividing a frequency band corresponding to an analog input signal Sx into N parts, the analog-to-digital converter comprising N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of the channels CHi, wherein i=1 to N and N is an integer; processing, by the N analog processing blocks Ai, analog signals of the channels CHi; processing, by N digital processing blocks Bi comprised by the analog-to-digital converter, digital signals of the channels CHi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi; and outputting, by an adder comprised by the analog-to-digital converter, a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis; wherein each analog processing block Aj of the N analog processing blocks Ai includes: a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1; and a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter; wherein j=2 to N; wherein each digital processing block Bj of the N digital processing blocks Bi includes: a multiplier configured to double a signal strength of a first digital signal S1j acquired by the sub A/D converter of the analog processing block Aj; a subtractor configured to: subtract a third digital signal S3j-1 relating to the channel CHj-1 from a second digital signal S2j acquired by the multiplier; and output a third digital signal S3j of a corresponding channel CHj; and a frequency converter configured to up-convert the third digital signal S3j to obtain an up-converted third digital signal S3j and outputs the up-converted third digital signal S3j to the adder as a channel output signal Syj of the corresponding channel CHj; wherein an analog processing block A1 of the N analog processing blocks Ai includes a sub A/D converter configured to A/D-convert, by a sub A/D converter of an analog processing block n the analog input signal Sx; and wherein a digital processing block B1 of the N digital processing blocks Bi outputs a first digital signal S11 acquired by the sub A/D converter of the analog processing block A1 as a third digital signal of a corresponding channel CH1 and also outputs the first digital signal S11 to the adder as a channel output signal Sy1 of the corresponding channel CH1. Claim: 11. The method according to claim 10, wherein the N digital processing blocks Bi each include a digital filter configured to compensate for a frequency characteristic in a corresponding partial band Wi in a band of a first output signal Si1 from an analog processing block Ai of the respective one of the channels CHi based on an inverse transfer function of a signal path through the analog processing block Ai. Current International Class: 03

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Analog/Digital Converter