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An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

Titel:	APPLICATIONS OF BACK-END-OF-LINE (BEOL) CAPACITORS IN COMPUTE-IN-MEMORY (CIM) CIRCUITS
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2022
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20220012581 Publication Date: January 13, 2022 Appl. No: 17/484828 Application Filed: September 24, 2021 Claim: 1. A computing system, comprising: a network interface; a peripheral controller; a main memory; a semiconductor chip having a compute-in-memory (CIM) circuit to implement a neural network, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising a switched capacitor circuit, the switched capacitor circuit comprising a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Claim: 2. The apparatus of claim 1 wherein the memory array comprises a static random access memory (SRAM) memory array. Claim: 3. The apparatus of claim 2 wherein the BEOL capacitor and thin film transistor are located above the SRAM memory array. Claim: 4. The apparatus of claim 3 wherein the mathematical computation circuit is to accumulate values read from the memory array. Claim: 5. The apparatus of claim 3 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array. Claim: 6. The apparatus of claim 1 wherein the mathematical computation circuit is to accumulate values read from the memory array. Claim: 7. The apparatus of claim 1 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array. Claim: 8. An apparatus, comprising: a network interface; a peripheral controller; a main memory; a semiconductor chip having a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip, the CIM circuit comprising a mathematical computation circuit coupled to a memory array, the mathematical computation circuit comprising an accumulation circuit, the accumulation circuit comprising a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors. Claim: 9. The apparatus of claim 8 wherein the memory array comprises a static random access memory (SRAM) memory array. Claim: 10. The apparatus of claim 9 wherein the ferroelectric BEOL capacitor is located above the SRAM memory array. Claim: 11. The apparatus of claim 10 wherein the mathematical computation circuit is to accumulate values read from the memory array. Claim: 12. The apparatus of claim 10 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array. Claim: 13. The apparatus of claim 8 wherein the mathematical computation circuit is to accumulate values read from the memory array. Claim: 14. The apparatus of claim 8 wherein the mathematical computation circuit is to multiply and accumulate values read from the memory array. Claim: 15. The apparatus of claim 8 wherein ferroelectric material of the ferroelectric BEOL capacitor comprises grain sizes less than 3 nm and/or is amorphous. Claim: 16. The apparatus of claim 8 wherein the ferroelectric BEOL capacitor comprises material selected from the group consisting of: hafnium zirconium oxide; hafnium oxide; zirconium oxide; hafnium aluminum oxide; hafnium silicon oxide; hafnium zirconium aluminum oxide; hafnium zirconium silicon oxide; hafnium yttrium oxide; yttrium zirconium oxide; hafnium yttrium zirconium oxide. Claim: 17. The apparatus of claim 16 wherein the material is doped with yttrium. Claim: 18. The apparatus of claim 8 wherein the CIM circuit further comprises a switched capacitor circuit that comprises a circuit to sense a switch in dipole moment direction of the ferroelectric capacitor, wherein, the sense of the switch is to determine an accumulate value. Claim: 19. The apparatus of claim 18 wherein the circuit is a current sensing circuit. Current International Class: 06; 01; 01; 06; 06; 01; 11; 11

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APPLICATIONS OF BACK-END-OF-LINE (BEOL) CAPACITORS IN COMPUTE-IN-MEMORY (CIM) CIRCUITS