Einzeltreffer — DigiBib

A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.

Titel:	COMPUTE IN MEMORY (CIM) MEMORY ARRAY
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2022
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20220375508 Publication Date: November 24, 2022 Appl. No: 17/561106 Application Filed: December 23, 2021 Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsinchu, TW) Claim: 1. A memory device for compute-in-memory (CIM), comprising: a memory array including a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells; a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line; and a control circuit configured to select the first group of memory cells and/or the second group of memory cells in response to a group enable signal. Claim: 2. The memory device of claim 1, further comprising: a first sense amplifier coupled to the bit lines of the first group of memory cells; and a second sense amplifier coupled to the bit lines of the second group of memory cells. Claim: 3. The memory device of claim 2, further comprising a multiplexer (MUX) connected to the first sense amplifier and the second sense amplifier. Claim: 4. The memory device of claim 1, wherein each of the memory cells includes one transistor and one capacitor for form a one-transistor one capacitor (1T-1C) memory cell. Claim: 5. The memory device of claim 4, wherein the transistor of the 1T-1C memory cell includes a gate terminal connected to its respective word line. Claim: 6. The memory device of claim 4, wherein the transistor of the 1T-1C memory cell includes: a first source/drain (S/D) terminal connected to its respective bit line; and a second source/drain (S/D) terminal connected to a first terminal of the capacitor of the 1T-1C. Claim: 7. The memory device of claim 4, wherein the memory array includes a power input terminal configured to receive a VDD voltage, and wherein the capacitor of the 1T-1C memory cell includes a second terminal connected to receive a half VDD voltage. Claim: 8. The memory device of claim 1, wherein the memory cells further include a third group of memory cells and a fourth group of memory cells. Claim: 9. The memory device of claim 8, wherein the control circuit is configured to select the first and third groups of memory cells or the second and fourth groups of memory cells in response to a one-bit group enable signal. Claim: 10. The memory device of claim 8, wherein the control circuit is configured to select the first group, the second group, the third group or the fourth group of memory cells in response to a two-bit group enable signal. Claim: 11. The memory device of claim 1, wherein the control circuit includes: a first control circuit connected to the bit lines of the first column; and a second control circuit connected to the bit lines of the second column. Claim: 12. A compute in memory (CIM) device, comprising: a plurality of memory cells configured to store weight signals, the memory cells arranged in an array of rows and columns including a first group of memory cells and a second group of memory cells; a plurality of word lines, each row of the array having a corresponding word line, each memory cell coupled to the corresponding word line; a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell coupled to the corresponding bit line; a sense amplifier coupled to the bit lines and configured to amplify signals of the bit lines for reading operations; a control circuit connected to the bit lines and configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal; an input terminal configured to receive a CIM input signal; and a multiply circuit configured to multiply the weight signals by the CIM input signal to generate a plurality of partial products. Claim: 13. The CIM device of claim 12, further comprising a multiplexer (MUX) connected to the sense amplifier. Claim: 14. The CIM device of claim 12, wherein each of the memory cells includes one transistor and one capacitor for form a one-transistor one capacitor (1T-1C) memory cell. Claim: 15. The CIM device of claim 12, wherein the memory cells further include a third group of memory cells and a fourth group of memory cells. Claim: 16. The CIM device of claim 12, further comprising a one IO adder tree circuit configured to add the plurality of partial products. Claim: 17. A method, comprising: providing a memory array having a plurality of memory cells arranged in an array of rows and columns, the memory cells including a first group of memory cells and a second group of memory cells; providing a plurality of word lines, each row of the array having a corresponding word line, each memory cell of a row of the array coupled to the corresponding word line; providing a plurality of bit lines, each column of the array having a corresponding bit line, each memory cell of a column of the array coupled to the corresponding bit line; receiving a group enable signal; performing a first operation on the first group of memory cells in response to the group enable signal; and performing a second operation on the second group of memory cells in response to the group enable signal. Claim: 18. The method of claim 17, wherein the first operation is a read operation and the second operation is a write operation. Claim: 19. The method of claim 17, wherein the first operation and the second operation are performed simultaneously. Claim: 20. The method of claim 17, further comprising: writing compute in memory (CIM) weight signals to the memory cells; reading the CIM weight signals from the memory cells; receiving a CIM input signal; and multiplying the CIM input signal by the CIM weight signals by a multiply circuit. Current International Class: 11; 11; 11; 06

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COMPUTE IN MEMORY (CIM) MEMORY ARRAY