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- Nachgewiesen in: USPTO Patent Applications
- Sprachen: English
- Document Number: 20230260569
- Publication Date: August 17, 2023
- Appl. No: 17/670384
- Application Filed: February 11, 2022
- Claim: 1. A memory device, comprising: a memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows, wherein the memory cells in each of the plurality of columns comprise first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns; a first computation circuit coupled to the first memory cells in each of the plurality of columns, and configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells; and a second computation circuit coupled to the second memory cells in each of the plurality of columns, and configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.
- Claim: 2. The memory device of claim 1, further comprising a plurality of word lines, wherein the plurality of rows in the memory array comprises first rows of the first memory cells and second rows of the second memory cells, the first rows and the second rows are alternately arranged along the column direction, and each of the plurality of word lines is coupled to the first memory cells in one of the first rows and the second memory cells in an adjacent one of the second rows.
- Claim: 3. The memory device of claim 1, wherein the first computation circuit and the second computation circuit comprise analog Multiply Accumulate (MAC) circuits.
- Claim: 4. The memory device of claim 1, wherein the first computation circuit and the second computation circuit comprise digital Multiply Accumulate (MAC) circuits.
- Claim: 5. The memory device of claim 1, further comprising a plurality of bit lines including: first bit lines each coupling the first memory cells in a corresponding column among the plurality of columns to the first computation circuit, and second bit lines each coupling the second memory cells in a corresponding column among the plurality of columns to the second computation circuit.
- Claim: 6. The memory device of claim 1, further comprising N read word lines and 2N write word lines, where N is a natural number, wherein the plurality of rows in the memory array comprises N first rows of the first memory cells and N second rows of the second memory cells, the N first rows and the N second rows are alternately arranged along the column direction, each of the N read word lines is coupled to the first memory cells in one of the N first rows and the second memory cells in an adjacent one of the N second rows, and each of the 2N write word lines is coupled either to the first memory cells in one of the N first rows or the second memory cells in one of the N second rows.
- Claim: 7. The memory device of claim 1, further comprising a third computation circuit and a fourth computation circuit, wherein the memory cells in each of the plurality of columns further comprise third memory cells and fourth memory cells, the first through fourth memory cells are alternately arranged in each of the plurality of columns, the third computation circuit is coupled to the third memory cells in each of the plurality of columns, and configured to generate third output data corresponding to a third computation performed on third weight data stored in the third memory cells; and the fourth computation circuit is coupled to the fourth memory cells in each of the plurality of columns, and configured to generate fourth output data corresponding to a fourth computation performed on fourth weight data stored in the fourth memory cells.
- Claim: 8. The memory device of claim 7, further comprising a plurality of word lines, wherein the plurality of rows in the memory array comprises first rows of the first memory cells, second rows of the second memory cells, third rows of the third memory cells, and fourth rows of the fourth memory cells, the first through fourth rows are alternately arranged along the column direction, and the plurality of word lines comprises: at least one first word line coupled to the first memory cells in one of the first rows and the second memory cells in an adjacent one of the second rows, and at least one second word line coupled to the third memory cells in one of the third rows and the fourth memory cells in an adjacent one of the fourth rows.
- Claim: 9. The memory device of claim 8, wherein the at least one first word line is coupled to the at least one second word line.
- Claim: 10. The memory device of claim 1, wherein the memory array is arranged, along the column direction, between the first computation circuit and the second computation circuit.
- Claim: 11. (canceled)
- Claim: 12. A memory device, comprising: a memory array comprising a plurality of memory cells configured to store weight data for a computing-in-memory (CIM) operation, wherein the plurality of memory cells comprises 2K memory cell groups, where K is a natural number, each of the 2K memory cell groups comprises at least one row of memory cells, and the rows of memory cells of the 2K memory cell groups are alternately arranged along a column direction; 2K Multiply Accumulate (MAC) circuits each coupled to the memory cells of a corresponding memory cell group among the 2K memory cell groups, and configured to generate output data corresponding to a computation performed on the weight data stored in the memory cells of the corresponding memory cell group; and a plurality of read word lines each coupled to the memory cells in at least two rows belonging to two different memory cell groups among the 2K memory cell groups.
- Claim: 13. The memory device of claim 12, wherein at least two rows are adjacent along the column direction.
- Claim: 14. The memory device of claim 12, wherein a pair of adjacent read word lines among the plurality of read word lines are coupled together.
- Claim: 15. The memory device of claim 12, wherein the plurality of memory cells of the memory array are arranged in a plurality of columns along the column direction, and the memory device further comprises, for each of the plurality of columns, 2K read bit lines each coupling the memory cells of one of the 2K memory cell groups to the corresponding MAC circuit.
- Claim: 16. The memory device of claim 15, further comprising: for each of the plurality of columns, at least one write bit line coupled to the memory cells of all 2K memory cell groups in said column.
- Claim: 17. The memory device of claim 15, further comprising: a plurality of write word lines each coupled to one corresponding row among the rows of memory cells.
- Claim: 18. A method of operating a memory device, the method comprising: simultaneously accessing adjacent first and second rows of memory cells in the memory device, through a common read word line coupled to the first and second rows of memory cells; and performing a first computing-in-memory (CIM) operation using first weight data read from the accessed memory cells of the first row, and a second CIM operation using second weight data read from the accessed memory cells of the second row.
- Claim: 19. The method of claim 18, wherein the first and second CIM operations are independent from each other.
- Claim: 20. The method of claim 18, wherein the first and second CIM operations are performed simultaneously.
- Claim: 21. The memory device of claim 1, wherein in each of the plurality of columns, at least one of the first memory cells is arranged between two of the second memory cells.
- Current International Class: 11; 11; 06
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