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A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.

Titel:	METHOD FOR MASK DATA SYNTHESIS WITH WAFER TARGET ADJUSTMENT
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20240061344 Publication Date: February 22, 2024 Appl. No: 18/499955 Application Filed: November 01, 2023 Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu, TW) Claim: 1. A method for manufacturing a lithographic mask for an integrated circuit, comprising: generating a database, comprising: generating a plurality of integrated circuit layout patterns; performing mask projection of each one of the integrated circuit layout patterns to generate a corresponding pattern; and storing the integrated circuit layout patterns and the corresponding patterns in the database stored in a storage memory; training a convolutional neural network based on a first portion of the database, wherein the integrated circuit layout patterns are inputs of the convolutional neural network and the corresponding patterns are outputs of the convolutional neural network; verifying the convolutional neural network based on a remaining second portion of the database; receiving a first integrated circuit layout pattern; generating, as an output of the convolutional neural network and based on the first integrated circuit layout pattern, a first pattern as a pattern when the first integrated circuit layout pattern is projected on a wafer; and inspecting the first pattern to verify the first integrated circuit layout pattern. Claim: 2. The method of claim 1, wherein the generated first pattern comprises one or more parameters of the first pattern, and wherein the verifying the first integrated circuit layout pattern further comprises: verifying the one or more parameters are within a process window, wherein the process window comprises a threshold range of radiation energy for generating the first pattern and a depth of focus threshold range for the generated first pattern. Claim: 3. The method of claim 2, further comprising: performing two or more mask projections for each one of a plurality of first integrated circuit layout patterns to generate two or more corresponding patterns for each one of the first integrated circuit layout patterns, wherein the two or more mask projections have different exposure doses and different depth of focus conditions. Claim: 4. The method of claim 3, wherein the first integrated circuit layout pattern comprises a corresponding exposure dose and a corresponding depth of focus for generating the first integrated circuit layout pattern, the method further comprising: verifying the corresponding exposure dose and the corresponding depth of focus are within the process window. Claim: 5. The method of claim 1, wherein the verifying the first integrated circuit layout pattern does not generate defects when verifying a probability of generating a defect in the first pattern is below a first threshold level. Claim: 6. The method of claim 1, wherein first integrated circuit layout pattern comprises a graphic design system (GDS) file. Claim: 7. The method of claim 1, wherein the performing the mask projection is a simulation projection. Claim: 8. The method of claim 1, further comprising: performing an optical proximity correction (OPC) process and an inverse lithographic technology (ILT) process to the first integrated circuit layout pattern to produce an OPC-ILT-enhanced mask layout; and verifying the OPC-ILT-enhanced mask layout using the convolutional neural network. Claim: 9. The method of claim 1, wherein the inspecting the first pattern comprises: verifying that the first pattern does not generate defects. Claim: 10. A system for manufacturing a lithographic mask for an integrated circuit, comprising: an optical proximity correction-inverse lithographic technology enhancer (OPC-ILT) module configured to perform an optical proximity correction to a mask layout to produce a corrected mask layout; and perform an inverse lithographic technology process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout; a convolutional neural network configured to: receive the OPC-ILT enhanced mask layout; and generate a pattern when the integrated circuit layout pattern is projected on a wafer; and a training module configured to: train the convolutional neural network using a training data set stored in a first portion of a database; and verify the convolutional neural network using a verification data set stored in a second portion of the database. Claim: 11. The system of claim 10, wherein the training module is further configured to: receive a plurality of mask layouts; receive patterns corresponding to each one of mask layouts; and store the plurality mask layouts and the corresponding patterns in the first portion of the database. Claim: 12. The system of claim 11, further comprising: a mask design module configured to generate the mask layout. Claim: 13. The system of claim 12, further comprising: a mask projection system configured to use a radiation source to project the mask layout on a mask-blank to produce a lithographic mask. Claim: 14. A method for manufacturing a lithographic mask for an integrated circuit, comprising: generating a plurality of integrated circuit layout patterns; performing mask projection of each one of the integrated circuit layout patterns to generate a corresponding pattern; storing the integrated circuit layout patterns and the corresponding patterns in a database stored in a memory; training a convolutional neural network using a training data set stored in the database; verifying the convolutional neural network using a verification data set stored in the database; generating, as an output of the convolutional neural network and based on a first integrated circuit layout pattern, a first pattern when the first integrated circuit layout pattern is projected on a wafer; performing an optical proximity correction (OPC) process and an inverse lithographic technology (ILT) process to the first integrated circuit layout pattern to produce an OPC-ILT-enhanced mask layout; and verifying the OPC-ILT-enhanced mask layout using the convolutional neural network. Claim: 15. The method of claim 14, further comprising receiving the integrated circuit layout patterns from a mask design module. Claim: 16. The method of claim 14, further comprising storing the OPC-ILT-enhanced mask layout in the database stored in the memory. Claim: 17. The method of claim 16, further comprising training the convolutional neural network based on the database stored in the memory. Claim: 18. The method of claim 14, wherein the first integrated circuit layout pattern comprises a graphic design system (GDS) file, and wherein the OPC-ILT-enhanced mask layout comprises an adjusted GDS file. Claim: 19. The method of claim 14, wherein the performing the mask projection is a simulation projection. Claim: 20. The method of claim 14, wherein the first integrated circuit layout pattern comprises a corresponding exposure dose and a corresponding depth of focus for generating the first integrated circuit layout pattern, the method further comprising: verifying the corresponding exposure dose and the corresponding depth of focus are within the process window. Current International Class: 03; 06; 06; 06; 06; 06

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METHOD FOR MASK DATA SYNTHESIS WITH WAFER TARGET ADJUSTMENT