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- Nachgewiesen in: USPTO Patent Applications
- Sprachen: English
- Document Number: 20240096978
- Publication Date: March 21, 2024
- Appl. No: 17/946017
- Application Filed: September 15, 2022
- Claim: 1. A CMOS apparatus comprising: an interconnect layer, which has a front side and a backside opposite the front side; an n-doped field effect transistor (nFET), disposed at the backside of the interconnect layer, wherein the nFET comprises an nFET drain structure, an nFET source structure, and an nFET channel structure that is connected between the nFET drain structure and the nFET source structure, wherein the nFET has a front side surface adjacent the interconnect layer and a backside surface opposite the interconnect layer; a p-doped field effect transistor (pFET), disposed at the backside of the interconnect layer adjacent to the nFET, wherein the pFET comprises a pFET drain structure, a pFET source structure, and a pFET channel structure that is connected between the pFET drain structure and the pFET source structure, wherein the pFET has a front side surface adjacent the interconnect layer and a backside surface opposite the interconnect layer; and a backside drain contact, disposed at the backside surface of the nFET and the pFET and electrically connected to the nFET drain structure and to the pFET drain structure.
- Claim: 2. The CMOS apparatus of claim 1, wherein the backside drain contact comprises: a metal pillar disposed between, and directly contacting, adjacent facing surfaces of the nFET and pFET drain structures.
- Claim: 3. The CMOS apparatus of claim 2, wherein the backside drain contact further comprises: a metal bar, connected crosswise and contiguous to the metal pillar and directly contacting the backside surfaces of the nFET and pFET drain structures.
- Claim: 4. The CMOS apparatus of claim 2, wherein the backside drain contact further comprises: a metal bar, connected crosswise and contiguous to the metal pillar and directly contacting an entirety of the backside surfaces of the nFET and pFET drain structures.
- Claim: 5. The CMOS apparatus of claim 4, further comprising: shallow trench isolation at either side of the metal bar.
- Claim: 6. The CMOS apparatus of claim 2, further comprising an interlayer dielectric, disposed between the nFET and pFET drain structures and the interconnect layer, wherein the metal pillar extends beyond the nFET and pFET drain structures into the interlayer dielectric.
- Claim: 7. The CMOS apparatus of claim 1, further comprising: shallow trench isolation material at either side of the backside drain contact.
- Claim: 8. The CMOS apparatus of claim 1, wherein the gate stack comprises a gate-all-around gate structure between the source structures and the drain structures.
- Claim: 9. The CMOS apparatus of claim 1, wherein the gate stack comprises a forksheet gate structure between the source structures and the drain structures.
- Claim: 10. A method for making a CMOS apparatus, the method comprising: obtaining a precursor to the CMOS apparatus, wherein the precursor comprises: a backside dielectric; an nFET drain structure that contacts the backside dielectric; a pFET drain structure that is adjacent to the nFET drain structure on the backside dielectric, wherein the nFET drain structure and the pFET drain structure have adjacent facing surfaces; and a dielectric pillar that extends from the backside dielectric between and contacting adjacent facing surfaces of the adjacent drain structures; forming, in the backside dielectric, a trench that contacts backside surfaces of the adjacent drain structures, wherein forming the trench includes removing the dielectric pillar; and filling the trench, from the backside of the apparatus, with a conductive material such that the conductive material contacts the backside surfaces of the adjacent drain structures and also contacts the adjacent facing surfaces of the adjacent drain structures.
- Claim: 11. The method of claim 10, wherein obtaining the precursor comprises: forming a blank that has a substrate, a source portion, a drain portion, and a gate portion between the source portion and the drain portion, wherein each of the source portion, the drain portion, and the gate portion comprises a continuous stack of nanosheets stacked on the substrate, and each of the source portion, the drain portion, and the gate portion is split in half by a continuous dielectric pillar that extends through the source portion, the drain portion, and the gate portion; forming a dummy gate and a hard mask over the source, drain, and gate portions of the blank; removing the hard mask, the dummy gate, and the stack of nanosheets from the source portion of the blank and from the drain portion of the blank; indenting the source portion at each side of the dielectric pillar to a first depth below a top surface of the substrate; and indenting the drain portion at each side of the dielectric pillar to a second depth, deeper than the first depth, below the top surface of the substrate.
- Claim: 12. The method of claim 11, wherein the second depth is deeper than a bottom of the dielectric pillar.
- Claim: 13. The method of claim 11, further comprising: filling a sacrificial material into the indentations of the drain portion to a level that is flush with the top surface of the substrate.
- Claim: 14. The method of claim 13, further comprising: after filling the sacrificial material, epitaxially growing drain structures, from the nanosheets in the gate portion, at either surface of the dielectric pillar on the drain portion of the blank.
- Claim: 15. The method of claim 14, further comprising, before forming the trench in the backside dielectric, inverting the precursor.
- Claim: 16. The method of claim 15, further comprising, before inverting the precursor, bonding a carrier wafer to the blank.
- Claim: 17. The method of claim 16, further comprising, after inverting the precursor and before forming the trench, recessing the substrate of the precursor.
- Claim: 18. The method of claim 17, further comprising, after recessing the substrate, depositing a backside dielectric.
- Claim: 19. The method of claim 18, further comprising, before forming the trench, planarizing the backside dielectric flush with backside surfaces of the sacrificial material.
- Claim: 20. The method of claim 15, further comprising, before inverting the precursor: epitaxially growing source structures, from the nanosheets of the gate portion, on the source portion of the blank; and forming frontside contacts to the source structures.
- Current International Class: 01; 01; 01; 01; 01; 01; 01
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