Einzeltreffer — DigiBib

A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.

Titel:	MIXED-SIGNAL PROCESSING INTEGRATED IN HYBRID VOLTAGE-TIME ANALOG TO DIGITAL CONVERTER
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20240106452 Publication Date: March 28, 2024 Appl. No: 17/955186 Application Filed: September 28, 2022 Claim: 1. A converter comprising: a plurality of time-to-voltage converters (TVCs), a TVC of the plurality configured to receive an input time-domain signal, the input time-domain signal representing a different sample than input time-domain signals of other TVCs of the plurality of TVCs; and a capacitive element coupled to outputs of the plurality of TVCs to receive a combined output signal of the plurality of TVCs, the capacitive element providing an input capacitance of an analog-to-digital converter (ADC). Claim: 2. The converter of claim 1, wherein the converter provides input to a plurality of ADCs. Claim: 3. The converter of claim 1, wherein the ADC comprises a successive approximation (SAR) circuit configured to generate a digital-domain version of the combined output signal. Claim: 4. The converter of claim 1, wherein the plurality of TVCs is configured to generate the combined output signal by providing weighting factors to a plurality of input time-domain signals. Claim: 5. The converter of claim 4, wherein the weighting factors comprise weighted current values for the plurality of TVCs, and wherein the weighted current values may be controlled via a digital signal processor (DSP) and generate an output voltage proportional to capacitive values associated with the capacitive element. Claim: 6. The converter of claim 1, wherein the number of TVCs is greater than or equal to the number input time-domain signals. Claim: 7. The converter of claim 1, wherein the number of ADCs is equal to the number of input time-domain signals. Claim: 8. The converter of claim 1, wherein the plurality of TVCs are differential TVCs. Claim: 9. The converter of claim 1, wherein the time-domain signals are generated by providing a voltage-domain signal to a single voltage-to-time converter (VTC) and outputting a result of the VTC to a digital de-multiplexer to generate the time-domain signals. Claim: 10. The converter of claim 1, wherein the time-domain signals are generated by providing a voltage-domain signal to a plurality of time-interleaved voltage-to-time converters (VTCs) to generate the time-domain signals, and wherein the plurality of time-interleaved VTCs are driven by phase-shifted clocks. Claim: 11. The converter of claim 10, wherein the time-domain signals are sampled simultaneously from different voltage-domain signals. Claim: 12. The converter of claim 1, wherein the number of ADCs is greater than the number of input time-domain signals, and wherein the converter provides upsampling. Claim: 13. The converter of claim 1, wherein the number of ADCs is less than the number of input time-domain signals, and wherein the converter provides downsampling. Claim: 14. A device comprising: digital processing circuitry; and a converter comprising: a plurality of time-to-voltage converters (TVCs), a TVC of the plurality configured to receive an input time-domain signal, the input time-domain signal representing a different sample than input time-domain signals of other TVCs of the plurality of TVCs; and a capacitive element coupled to outputs of the plurality of TVCs to receive a combined output signal of the plurality of TVCs, the capacitive element providing an input capacitance of an analog-to-digital converter (ADC). Claim: 15. The device of claim 14, wherein the ADC comprises a successive approximation (SAR) circuit configured to generate a digital-domain version of the combined output signal. Claim: 16. The device of claim 14, wherein the plurality of TVCs is configured to generate the combined output signal by providing weighting factors to a plurality of input time-domain signals. Claim: 17. The device of claim 14, wherein the number of ADCs is greater than the number of input time-domain signals, and wherein the converter provides upsampling. Claim: 18. The device of claim 14, wherein the number of ADCs is less than the number of input time-domain signals, and wherein the converter provides downsampling. Claim: 19. A method for analog-to-digital conversion, the method comprising: providing a calibration input to converter circuitry; enabling one of a plurality of time-to-voltage converters (TVCs), the plurality providing input to an analog-to-digital converter (ADC); measuring response of an ADC of an array of ADCs to the one of the plurality of TVCs; and decoding the ADC response and providing a calibrated signal based on measured responses of the ADC to the plurality of TVCs. Claim: 20. The method of claim 19, further comprising: performing successive approximation to generate a digital-domain version of a combined output signal. Claim: 21. The method of claim 19, wherein providing a combined output signal further comprises providing weighting factors to a plurality of input time-domain signals. Current International Class: 03; 03

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MIXED-SIGNAL PROCESSING INTEGRATED IN HYBRID VOLTAGE-TIME ANALOG TO DIGITAL CONVERTER