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An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

Titel:	METHODS AND APPARATUS TO PERFORM CML-TO-CMOS DESERIALIZATION
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20240113713 Publication Date: April 4, 2024 Appl. No: 18/539381 Application Filed: December 14, 2023 Claim: 1. A system comprising: a first deserializer including an input, a first output and a second output, the input configured to receive a current-mode logic (CML) data stream; a first deserializer array coupled to the first deserializer, the first deserializer array including: a second deserializer including a first input and a third output, the first input coupled to the first output; and a third deserializer including a second input and a fourth output, the second input coupled to the third output; and a second deserializer array coupled to the first deserializer array, the second deserializer array including: a fourth deserializer including a third input and a fifth output and a sixth output, the third input coupled to the second output; and a fifth deserializer including a fourth input and a seventh output and an eight output, the fourth input coupled to the third output, and a complementary metal-oxide-semiconductor (CMOS) data stream is configured to be generated at each of the fifth, sixth, seventh and eight output. Claim: 2. The system of claim 1, wherein the first deserializer is configured to convert a CML data stream to a plurality of CML data streams. Claim: 3. The system of claim 1, wherein the second deserializer is configured to convert CML data stream to a plurality of CML data streams. Claim: 4. The system of claim 3, wherein the second deserializer further comprises: a first level shifting circuit; and one or more latches coupled to the first level shifting circuit. Claim: 5. The system of claim 4, wherein the first level shifting circuit further comprises: a first resistor coupled between a supply voltage terminal and a first latch; and a second resistor coupled between the first resistor, the first latch and a second latch. Claim: 6. The system of claim 5, wherein a first and a second input terminals of the second latch are coupled to a first and a second output terminals of the first latch, and a common mode level of the CML data stream received at the first latch is greater than a common mode level of the CML data stream generated by the second latch. Claim: 7. The system of claim 1, wherein the fourth deserializer is configured to convert CML data stream to a plurality of CMOS data streams. Claim: 8. The system of claim 7, wherein the fourth deserializer further comprises: a second level shifting circuit; one or more strongARM latches coupled to the second level shifting circuit; and one or more latches coupled to the one or more strongARM latches. Claim: 9. The system of claim 8, wherein the second level shifting circuit further comprises: a first and a second transistor coupled to a supply voltage terminal; a first resistor and a second resistor coupled to the first transistor and the second transistor respectively; a first current source coupled between the first resistor and a ground terminal; and a second current source coupled between the second resistor and the ground terminal. Claim: 10. The system of claim 9, wherein the strongARM latch further comprises: a first input terminal coupled to the first resistor and the first current source; and a second input terminal coupled to the second resistor and the second current source. Claim: 11. The system of claim 9, wherein and the second level shifting circuit receives the CML data stream and the strongARM latch generates the CMOS data stream. Claim: 12. A method comprising: configuring a first deserializer to generate a plurality of secondary current-mode logic (CML) data streams in response to a primary current-mode logic (CML) data stream; and configuring a second deserializer to generate two complementary metal-oxide-semiconductor (CMOS) data streams in response to a secondary CML data stream of the plurality of secondary CML data streams. Claim: 13. The method of claim 12, wherein configuring the first deserializer further comprises: generating a first level shifted voltage and a second level shifted voltage from a supply voltage; configuring a first latch to generate tertiary signals in response to the first level shifted voltage, the primary CML data stream and a clock signal; and configuring a second latch to generate the secondary CML data stream in response to the second level shifted voltage, the tertiary signals and the clock signal. Claim: 14. The method of claim 13, wherein generating the first level shifted voltage and the second level shifted voltage further comprises providing the supply voltage to a first level shifting circuit, the first level shifting circuit includes: a first resistor coupled between a supply voltage terminal and the first latch, the supply voltage terminal configured to receive the supply voltage; and a second resistor coupled between the first resistor, the first latch and the second latch. Claim: 15. The method of claim 12, wherein configuring the second deserializer further comprises: generating a third level shifted voltage from a supply voltage and the secondary CML data stream; configuring a first strongARM latch to generate the CMOS data stream in response to the third level shifted voltage and a clock signal; and configuring a second strongARM latch to generate the CMOS data stream in response to the third level shifted voltage and the clock signal. Claim: 16. The method of claim 15, wherein generating the third level shifted voltage further comprising providing the supply voltage to a second level shifting circuit, the second level shifting circuit includes: a first and a second transistor coupled to a supply voltage terminal, the supply voltage terminal configured to receive the supply voltage; a first resistor and a second resistor coupled to the first transistor and the second transistor respectively; a first current source coupled between the first resistor and a ground terminal; and a second current source coupled between the second resistor and the ground terminal. Claim: 17. The method of claim 16, wherein configuring the strongARM latch further comprises: coupling a first input terminal to the first resistor and the first current source; and coupling a second input terminal to the second resistor and the second current source. Claim: 18. The method of claim 15, wherein configuring the second deserializer further comprises: latching the CMOS data stream from the first strongARM latch in a first flip-flop; and latching the CMOS data stream from the second strongARM latch in a second flip-flop. Claim: 19. The method of claim 18 further comprising sampling an output of the first flip-flop at a first terminal of a third flip-flop on receiving the clock signal at a second terminal of the third flip-flop. Claim: 20. The method of claim 19, wherein the two CMOS data streams generated by the second deserializer further comprises: generating a CMOS data stream at an output terminal of the third flip-flop; and generating a CMOS data stream at an output terminal of the second flip-flop. Current International Class: 03; 03

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METHODS AND APPARATUS TO PERFORM CML-TO-CMOS DESERIALIZATION