Einzeltreffer — DigiBib

Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.

Titel:	SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20240136359 Publication Date: April 25, 2024 Appl. No: 18/488916 Application Filed: October 16, 2023 Claim: 1. A synaptic array structure includes: a semiconductor substrate; an isolation insulating layer positioned in a predetermined area on the semiconductor substrate to isolate devices; CMOS peripheral circuits including PMOSFET and NMOSFET devices provided on the semiconductor substrate; and a plurality of TFT-type synaptic devices arranged in an array on the isolation insulating layer; wherein, the TFT-type synaptic device includes: a source and drain positioned on the isolation insulating layer and spaced apart from each other by a predetermined distance, and made of a semiconductor material doped with a first type of impurities; a semiconductor body positioned between the source and the drain and made of a semiconductor material doped with a second type of impurities opposite to the first type; oxide layers positioned between the semiconductor body and the source and between the semiconductor body and the drain; a semiconductor layer for channel positioned on the upper surfaces of the semiconductor body and oxide layers, configured to electrically connect the source and the drain by forming a channel, and made of a semiconductor material; a TFT gate insulating layer positioned on the upper surface of the semiconductor layer for channel and comprising of at least one insulating layer; and a TFT gate electrode positioned on the upper surface of the TFT gate insulating layer and made of a conductive material. Claim: 2. The synaptic array structure according to claim 1, wherein the thickness of the gate electrodes of the PMOSFET and NMOSFET devices of the CMOS peripheral circuit is thicker than the thickness of the source and drain of the TFT-type synaptic device. Claim: 3. The synaptic array structure according to claim 1, wherein the TFT gate electrode of the TFT-type synaptic device is provided in a self-aligned form with the source and drain of the TFT-type synaptic device. Claim: 4. The synaptic array structure according to claim 1, wherein the synaptic array structure implements an AND-type synaptic array architecture by arranging the source and drain lines for TFT-type synaptic devices in parallel, or a NOR-type synaptic array architecture by arranging orthogonally the source and drain lines of the TFT-type synaptic devices. Claim: 5. The synaptic array structure according to claim 1, wherein the synaptic array structure implements a NAND-type synaptic array architecture by connecting TFT-type synaptic devices in series to form cell strings and by connecting word lines to the TFT gate electrodes of TET-type synaptic devices, and wherein the synaptic array structure further includes at least one switch device at each end of the cell strings. Claim: 6. The synaptic array structure according to claim 1, wherein the TFT gate insulating layer has a stack structure including at least a charge storage layer and an insulating layer. Claim: 7. The synaptic array structure according to claim 1, wherein the semiconductor body is configured to have different heights from the source and drain to have steps in the edges of the oxide layers connecting between the semiconductor body and the source and between the semiconductor body and the drain, and the semiconductor layer for channel on surface of the oxide layer is curved by the steps formed in the edges of the oxide layers, so that a short channel effect is suppressed by changing the effective length of the semiconductor layer for channel due to forming a curved channel. Claim: 8. The synaptic array structure according to claim 7, wherein the upper surface of the semiconductor body is formed higher than the upper surfaces of the source and drain. Claim: 9. The synaptic array structure according to claim 1, wherein the semiconductor body is made of a semiconductor material doped with P-type impurities and is configured to provide holes to the semiconductor layer for channel during an erase operation, thereby reducing a erase voltage VERS required during the erase operation for selected cells or being capable of performing the erase operation with only positive (+) bias voltage, and suppressing the erase operation for unselected cells. Claim: 10. The synaptic array structure according to claim 1, wherein the source or drain of the TFT-type synaptic device and the TFT gate electrode of the TFT-type synaptic device are provided to overlap each other, and the TFT gate insulating layer provided between the overlapping source and the TFT gate electrode or between the overlapping drain and the TFT gate electrode is used as a capacitor. Claim: 11. A method of fabricating a synaptic array structure having TFT-type synaptic devices and CMOS peripheral circuits includes the following steps: (a) forming a well for fabricating devices of the CMOS peripheral circuit in a first predetermined area in the semiconductor substrate and forming an isolation insulating layer for isolating the devices in a second predetermined area in the semiconductor substrate; (b) forming a semiconductor body doped with a first type of impurities on the isolation insulating layer and forming an oxide layer on the surface of the semiconductor body; (c) depositing a semiconductor material doped with a second type of impurities on the entire surface and then planarizing the upper surface of the deposited semiconductor material to expose the upper surface of the semiconductor body of the TFT-type synaptic device; (d) forming the source and drain of the TFT-type synaptic device, and forming the gate electrodes of an NMOSFET and a PMOSFET devices of the CMOS peripheral circuit; (e) forming the source and drain of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit; (f) sequentially forming a semiconductor layer for channel and a TFT gate insulating layer on the upper surface of the TFT-type synaptic device; and (g) forming a TFT gate electrode and an electrode of a capacitor of the TFT-type synaptic device, wherein the TFT-type synaptic device and the NMOSFET and PMOSFET devices of the CMOS peripheral circuit share the fabrication process steps. Claim: 12. The method of fabricating the synaptic array structure according to claim 11, wherein the step (d) is comprising of: (d1) forming the source and drain of the TFT-type synaptic device and simultaneously forming the gate electrodes of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit using a photolithography process; and (d2) partially etching the source and drain of the TFT-type synaptic device without using additional masks, wherein the semiconductor body of the TFT-type synaptic device is formed to be higher than the source and drain of the TFT-type synaptic device. Claim: 13. The method of fabricating the synaptic array structure according to claim 12, wherein in the process of step (d1), a material for fabricating the gate electrodes of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit are deposited in the form of a thin film, and are deposited on the gate insulating layers of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit and on the isolation insulating layer formed higher than the upper surface of the gate insulating layers of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit, and the source and drain electrodes of the TFT-type synaptic device and the gate electrodes of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit are planarized and patterned using a chemical-mechanical polishing process so that the thickness of the source and drain electrodes of the TFT-type synaptic device is configured to be thinner than that of the gate electrodes of the NMOSFET and PMOSFET devices of the CMOS peripheral circuit. Current International Class: 01; 01

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SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE