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Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Titel:	SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER
Link:	View record in USPTO Patent Applications (Volltext)
Veröffentlichung:	2024
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20240153813 Publication Date: May 9, 2024 Appl. No: 18/403866 Application Filed: January 04, 2024 Claim: 1. A method, comprising: forming a layer of single crystal silicon germanium onto a surface of a silicon substrate; epitaxially growing the silicon germanium to form a thicker single crystal silicon germanium layer; forming a layer of single crystal silicon onto a surface of the thicker single crystal silicon germanium layer; epitaxially growing the single crystal silicon to form a thicker single crystal silicon layer; and forming, in repeating iterations, a number of additional layers of single crystal silicon germanium and single crystal silicon to form a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers. Claim: 2. The method of claim 1, further comprising, processing the vertical stack to expose a first surface of a first layer of single crystal silicon germanium and a first surface of a second layer of single crystal silicon germanium. Claim: 3. The method of claim 2, further comprising, forming a hard mask material on the first surface of the first layer of single crystal silicon germanium. Claim: 4. The method of claim 3, further comprising, forming a bonding material on the first surface of the second layer of single crystal silicon germanium. Claim: 5. The method of claim 4, further comprising, bonding the bonding material to a surface of a different substrate having a number of CMOS components formed thereon. Claim: 6. The method of claim 5, wherein the different substrate has a bonding material formed on a surface thereof, and wherein the method further comprises bonding the bonding material formed on the surface of the different substrate to the bonding material formed on the first surface of the second layer of single crystal silicon germanium. Claim: 7. The method of claim 1, further comprising, bonding the vertical stack to a different substrate having CMOS components formed thereon, the different substrate being processed separately from the substrate on which the vertical stack is formed. Claim: 8. The method of claim 1, further comprising forming vertical dynamic random access memory (DRAM) cells in the vertical stack. Claim: 9. The method of claim 8, further comprising forming access devices of the DRAM cells to have single crystal silicon channels. Claim: 10. A method, comprising: forming a first layer of single crystal silicon germanium onto a surface of a first substrate; forming a first layer of single crystal silicon onto a surface of the single crystal silicon germanium; forming, in repeating iterations, a number of additional layers of single crystal silicon germanium and single crystal silicon to form a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers; and bonding a surface of the vertical stack to a second substrate. Claim: 11. The method of claim 10, wherein the second substrate comprises a number of CMOS components formed thereon, and wherein the method further comprises: bonding the first substrate to the second substrate subsequent to forming the vertical stack. Claim: 12. The method of claim 11, wherein the temperature range used for the formation of the vertical stack is 600 degree Celsius (° C.) to 1100° C. Claim: 13. The method of claim 11, wherein the first layer of single crystal silicon germanium serves as a seed layer, and wherein the method includes heating the first layer of single crystal silicon germanium to increase a thickness of the first layer of single crystal silicon germanium via epitaxial growth. Claim: 14. The method of claim 13, wherein the seed layer has a thickness of about 100 Angstroms. Claim: 15. The method of claim 14, wherein the thickness of the first layer of single crystal silicon germanium is about 1,000 Angstroms after the epitaxial growth. Claim: 16. The method of claim 11, wherein the first layer of single crystal silicon serves as a seed layer, and wherein the method includes heating the first layer of single crystal silicon to increase a thickness of the first layer of single crystal silicon via epitaxial growth. Claim: 17. The method of claim 16, wherein the seed layer has a thickness of about 50 Angstroms. Claim: 18. The method of claim 17, wherein the thickness of the first layer of single crystal silicon is about 300 Angstroms after the epitaxial growth. Claim: 19. A method, comprising: forming a vertical stack of repeating iterations of single crystal silicon germanium and single crystal silicon layers on a substrate, wherein the vertical stack includes at least two iterations, and wherein forming each iteration comprises: forming a seed layer of single crystal silicon germanium; epitaxially growing single crystal silicon germanium from the seed layer of crystal silicon germanium to a desired first thickness; forming a seed layer of single crystal silicon onto a surface of the epitaxially grown single crystal silicon germanium; and epitaxially growing single crystal silicon from the seed layer of single crystal silicon to a desired second thickness; and forming dynamic random access memory cells in the vertical stack. Claim: 20. The method of claim 19, wherein the method includes bonding the substrate to a different substrate prior to forming the memory cells in the vertical stack. Current International Class: 01; 01; 01; 01

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SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER