Einzeltreffer — DigiBib

A ring oscillator has its inverter states in respective inner stages change at a time unit longer than a period of a master clock MCK and is oscillated at a period longer than the period of the master clock MCK. The inverter states of the respective stages of the ring oscillator are captured by a flipflop circuit and a value indicating each of these states is subtracted by a subtractor from numerical figures indicating the inverter states in the respective stages of the ring oscillator as captured at the timing of the master clock MCK by other flipflop circuits. The difference is output as a signal indicating the position of the input signal edge.

Titel:	Digital PLL circuit having signal edge position measurement
Autor/in / Beteiligte Person:	Fukuda, Shinichi
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	1995
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 5,428,648 Publication Date: June 27, 1995 Appl. No: 08/118,591 Application Filed: September 10, 1993 Assignees: Sony Corporation (Tokyo, JPX) Claim: What is claimed is Claim: 1. An input signal edge time measurement circuit comprising Claim: a ring oscillator having an odd number of inverters connected in a ring Claim: means for detecting an edge of an input signal Claim: first latch means for capturing first states of various respective stages of said ring oscillator at a timing of a detected edge of said input signal Claim: second latch means for capturing second states of said respective stages of said ring oscillator at the a timing of a master clock, and Claim: edge position calculating means for comparing said first states of said respective stages of said ring oscillator captured by said first latch means and said second states of said respective stages of said ring oscillator captured by said second latch means and outputting a difference between these states as an edge position detection signal. Claim: 2. The input signal edge time measurement circuit as claimed in claim 1 wherein said edge position calculating means comprise third latch means for capturing an output of said first latch means at a rise timing of said master clock and a fourth latch means for capturing an output of said first latch means at a decay timing of said master clock, and wherein an output of said third latch means and an output of said fourth latch means are selected when the edge of said input signal is in a high level domain of said master clock and in a low level domain of said master clock, respectively, and one of the output of said third latch means and the output of said fourth latch means thus selected is compared to an output of said second latch means. Claim: 3. The input signal edge time measurement circuit as claimed in claim 1 wherein said ring oscillator comprises inverter elements with variable delay and wherein said delay is switchingly selected responsive to ratio of period of oscillation of said ring oscillator to a period of said master clock. Claim: 4. An input signal time measurement circuit comprising Claim: a first edge detecting means for detecting an edge of input signals Claim: first latch means for capturing first states of various respective stages of said ring oscillator at a timing of said detected edge of an input signal Claim: second latch means for capturing second states of said respective stages of said ring oscillator at a timing of a master clock Claim: edge position calculating means for comparing said first states of said respective stages of said ring oscillator captured by said first latch means and said second states of said respective stages of said ring oscillator captured by said second latch means and outputting a difference between these states as an edge position detection signal Claim: a second edge detecting means for sampling said input signal with said master clock and detecting an input signal edge within a period of said master clock as a basis for outputting an edge detection signal Claim: reproducing clock generating means for outputting a reproducing clock based on phase error data and reproducing clock period data Claim: phase error detection means for finding phase error data between a reproducing clock edge and said input signal edge based on said edge position detection signal from said position calculating means and said edge detection signal from said second edge detecting means and transmitting said phase error data to said reproducing clock generating means, and Claim: reproducing clock period detection means for detecting period data of said reproducing clock from said reproducing clock generating means and transmitting said period data to said reproducing clock generating means. Claim: 5. The input signal edge time measurement circuit as claimed in claim 4 wherein said edge position calculating means comprise third latch means for capturing an output of said first latch means at a rise timing of said master clock and a fourth latch means for capturing an output of said first latch means at a decay timing of said master clock, and wherein an output of said third latch means and an output of said fourth latch means are selected when the edge of said input signal is in a high level domain of said master clock and in a low level domain of said master clock, respectively, and the output thus selected is compared to an output of said second latch means. Claim: 6. The input signal edge time measurement circuit as claimed in claim 4 wherein said ring oscillator comprises inverter elements with variable delay and wherein said delay is switchingly selected responsive to a ratio of a period of oscillation of said ring oscillator to a period of said master clock. Claim: 7. A digital PLL circuit supplied with an edge detection signal obtained by detecting an edge of an input signal using a master clock and with an edge position signal indicating a position of said input edge relative to said master clock, comprising Claim: a first shift register for storing said edge detection signal Claim: a window circuit for limiting an output of said first shift register to a number of bits corresponding to one period of a reproducing clock Claim: a first latch circuit for capturing bits passed through said window circuit Claim: edge bit position detection means for detecting a presence of said input edge and a corresponding bit position thereof relative to said bits captured by said first latch circuit Claim: a second shift register for storing said edge position signal Claim: a selector for selecting an output of said second shift register by using said edge detection signal Claim: a second latch circuit for capturing an output of said selector, and Claim: means for subtracting a value corresponding to a zero phase error edge position from a combined output of an output of said edge bit position detection means and an output of said second latch circuit. Claim: 8. The digital PLL circuit as claimed in claim 7 further comprising Claim: a window generating circuit for calculating a window width of said window circuit, including a boundary determinator for calculating a window boundary at an intra-bit position of a bit of said first shift register which is closest to an input side of said first shift register and producing an output for selecting an output of said second shift register corresponding to said bit closest to said input side of said first shift register, a comparator for comparing said output of said second shift register and said intra-bit position of said window boundary, and a circuit for decoding from a result of comparison whether or not said bit closest to said input side of said first shift register is in the window and producing an output for controlling said window circuit. Claim: 9. A digital PLL circuit supplied with an edge detection signal obtained on detecting an edge of an input signal using a master clock and with an edge position signal indicating the position of said input edge relative to said master clock, comprising Claim: a window generating circuit for calculating a window width of said window circuit, and Claim: wherein said window generating circuit includes a boundary determinator for calculating a window boundary at an intra-bit position of a bit of said first shift register which is closest to an input side of said first shift register and producing an output for selecting an output of said second shift register corresponding to said bit closest to said input side of said first shift register, a comparator for comparing said output of said second shift register and said intra-bit position of said window boundary and a circuit for deciding from a result of comparison whether or not said bit closest to said input side of said first shift register in the window and producing an output for controlling said window circuit. Current U.S. Class: 375/371; 375/373 Current International Class: H04L 700 Patent References Cited: 3878473 April 1975 Furtney, Jr. ; 4456890 June 1984 Carickhoff ; 4841551 June 1989 Avaneas ; 4954824 September 1990 Yamada et al. ; 5023892 June 1991 Stoica ; 5077529 December 1991 Ghoshal et al. ; 5166959 November 1992 Chu et al. Other References: Patent Abstracts of Japan, vol. 13, No. 128 corres. to JP-1,019,826 (Fukuda). ; Patent Abstracts of Japan, vol. 13, No. 123, corres. to JP-63-292,825 (Fukuda). ; The article appearing in Electronic Components and Applications, vol. 9, No. 2, 1989 (Rosink). ; The article appearing in International Symposium on Circuits and Systems, vol. 4, May 1990 (Kajiwara et al.). Primary Examiner: Chin, Stephen Assistant Examiner: Bocure, Tesfaldet Attorney, Agent or Firm: Maioli, Jay H.

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Digital PLL circuit having signal edge position measurement