Einzeltreffer — DigiBib

A process within substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate. The process may be used to produce flip chips, ball grid array modules, column grid array modules, circuit boards, and attachment structures of the preceding components including information handling systems.

Titel:	Process for transferring material to semiconductor chip conductive pads using a transfer substrate
Autor/in / Beteiligte Person:	Fallon, Kenneth Michael ; Le Coz, Christian Robert ; Pierson, Mark Vincent
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	1999
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 5,872,051 Publication Date: February 16, 1999 Appl. No: 08/510,401 Application Filed: August 02, 1995 Assignees: International Business Machines Corporation (Armonk, NY) Claim: We claim Claim: 1. A method of producing a semiconductor chip, comprising the steps of Claim: forming a semiconductor integrated circuit having a wiring layer with an arrangement of electrically conductive pads, and a layer of dielectric material covering said wiring layer; Claim: forming openings in said layer of dielectric material adjacent said conductive pads to expose said pads; Claim: producing a transfer substrate having a first surface with a plurality of blind holes located therein in a mirror image arrangement corresponding to said arrangement of electrically conductive pads; Claim: locating a quantity of joining material provided in paste form on said first surface of said transfer substrate and substantially filling said blind holes therein; Claim: bringing said first surface of said transfer substrate into direct physical contact with said layer of dielectric material and aligning said plurality of blind holes having said joining material in paste form therein within said first surface with said openings in said dielectric material; Claim: heating said joining material in paste form and said electrically conductive pads to cause said joining material to adhere to said electrically conductive pads; and removing at least a portion of said transfer substrate from contact with said layer of dielectric material while leaving substantially all of said joining material attached to said electrically conductive pads, thereby producing a semiconductor chip. Claim: 2. The method of claim 1 in which Claim: the step of producing said transfer substrate with said plurality of blind holes includes producing a silicon plate and further includes selecting the depth and diameter of said blind holes in said first surface to provide substantially hemispherical depressions therein which are about 0.1 to about 0.5 mm in diameter and between about 10 and about 100% of said diameter in depth within said first surface; and Claim: said method further comprising the step of depositing titanium nitride within said blind holes prior to locating said joining material in paste form in said blind holes to reduce adhesion to said joining material in paste form when said joining material in paste form is heated. Claim: 3. A method of making an interconnect substrate, comprising the steps of Claim: forming an electronic substrate including a wiring layer having an arrangement of electrically conductive pads and a layer of dielectric material covering said electrically conductive pads of said wiring layer; Claim: forming openings in said layer of dielectric material adjacent said electrically conductive pads to expose said electrically conductive pads; Claim: producing a transfer substrate having a first surface with a plurality of blind holes therein located in a mirror image arrangement corresponding to said arrangement of electrically conductive pads; Claim: locating a quantity of joining material provided in paste form on said first surface of said transfer substrate and substantially filling said holes therein; Claim: bringing said first surface of said transfer substrate into direct physical contact with said layer of dielectric material and aligning said blind holes having said joining material in paste form therein within said first surface with said openings in said dielectric material; Claim: heating said joining material in paste form and said electrically conductive pads to cause said joining material to adhere to said electrically conductive pads; and Claim: removing at least a portion of said transfer substrate from contact with said layer of dielectric material while leaving substantially all of said joining material attached to said electrically conductive pads, thereby making an interconnect substrate. Claim: 4. The method of claim 3, further comprising the steps of Claim: providing an electronic component having an array of electrically conductive terminals on one surface in a mirror image arrangement corresponding to said arrangement of said electrically conductive pads of said electronic substrate and positioning said electrically conductive terminals of said electronic component adjacent said joining material adhering to said electrically conductive pads, thereby forming electrical and mechanical contact between said terminals and said electrically conductive pads. Claim: 5. The method of claim 4 further comprising the step of heating said conductive terminals and said joining material to attach said conductive terminals to said electrically conductive pads. Claim: 6. The method of claim 3 in which the step of forming an electronic substrate further includes inserting metal pins in through holes in said electronic substrate. Claim: 7. The method of claim 3 in which the step of forming an electronic substrate further includes attaching solder balls to said electrically conductive pads. Claim: 8. A method of making an interconnect substrate, comprising the steps of Claim: providing an electronic substrate including a wiring layer having an arrangement of electrically conductive pads and a layer of dielectric material covering said wiring layer; Claim: producing a transfer substrate having holes passing through said transfer substrate, said holes located in a mirror image arrangement corresponding to said arrangement of electrically conductive pads; Claim: bringing said transfer substrate into direct physical contact with said layer of dielectric material and aligning said holes with said openings; Claim: thereafter depositing joining material in paste form into and substantially filling said holes, and into contact with said electrically conductive pads; Claim: removing said transfer substrate from contact with said layer of dielectric material while leaving substantially all of said joining material attached to said electrically conductive pads, thereby making an interconnect substrate. Claim: 9. A process for producing an information handling system, comprising the steps of Claim: providing one or more enclosures having one or more processing units communicating with random access memory contained therein; Claim: forming an electronic substrate including a wiring layer having an arrangement of electrically conductive pads and a layer of dielectric material covering said wiring layer; Claim: locating a quantity of joining material provided in paste form on said first surface of said transfer substrate and substantially filling said plurality of blind holes therein; Claim: heating said joining material in paste form and said electrically conductive pads to cause said joining material to adhere to said electrically conductive pads; Claim: removing at least a portion of said transfer substrate from contact with said layer of dielectric material while leaving substantially all of said joining material attached to said electrically conductive pads; thereby making an interconnect substrate; Claim: providing an electronic component having an array of electrically conductive terminals on one surface in a mirror image arrangement corresponding to said arrangement of said electrically conductive pads of said electronic substrate; Claim: positioning said electrically conductive terminals adjacent said joining material thereby forming electrical and mechanical contact between said terminals and said electrically conductive pads; and Claim: mounting said interconnect substrate within one of said enclosures and connecting said interconnect substrate to one or more of said processing units for handling information. Current U.S. Class: 438/616; 22818/022 Current International Class: H01L 21288; H01L 2158; H01L 2160 Patent References Cited: 3621564 November 1971 Shigezo et al. ; 3645392 February 1972 Chittenden et al. ; 3719981 March 1973 Steitz ; 4119480 October 1978 Nishi et al. ; 4311267 January 1982 Lim ; 4722470 February 1988 Johary ; 4752027 June 1988 Gschwend ; 4825034 April 1989 Axvert et al. ; 4914814 April 1990 Behun et al. ; 5024372 June 1991 Altman et al. ; 5057969 October 1991 Ameen et al. ; 5118027 June 1992 Braun et al. ; 5133495 July 1992 Angulas et al. ; 5145104 September 1992 Apap et al. ; 5196726 March 1993 Nishiguchi et al. ; 5203075 April 1993 Angulas et al. ; 5219117 June 1993 Lin ; 5261155 November 1993 Angulas et al. ; 5261593 November 1993 Cassoa ; 5275970 January 1994 Itoh et al. ; 5341564 August 1994 Akhavain et al. ; 5346118 September 1994 Degani et al. ; 5388327 February 1995 Trabucco ; 5468681 November 1995 Pasch ; 5492266 February 1996 Hoebener et al. ; 5539333 July 1996 Cao et al. ; 5542601 August 1996 Fallon et al. ; 5545465 August 1996 Gaynes et al. ; 5564617 October 1996 Degani et al. ; 5586715 December 1996 Schwiebert et al. ; 5597469 January 1997 Carey et al. ; 5607099 March 1997 Yeh et al. ; 5623506 April 1997 Dell et al. ; 5643831 July 1997 Ochiai et al. ; 5658827 August 1997 Aulicino et al. Other References: IBM Technical Disclosure Bulletin vol. 36 No. 02 Feb. 93' entitled "Solder Preform Technique for Fine Pitch Surface Mount Tech. Components" pp. 397-398. ; IBM Techincal Disclosure Bulletin vol. 37 No. 06B Jun. 94' entitled "Ball Grid Array and Column Grid Array Module Solder Stencil Template" pp. 225-226. ; IBM Technical Disclosure Bulletin vol. 20. No. 10 Mar. 78' entilted"Pinless Module Connector" pp. 3872. Primary Examiner: Graybill, David Attorney, Agent or Firm: Belk, Michael E. ; Pivnichny, John R.

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Process for transferring material to semiconductor chip conductive pads using a transfer substrate