Einzeltreffer — DigiBib

A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprises the steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said region are then divided into segments suitable for approximating lumped transmission-line LKR and relevant parameters determined so that time delays over each such segment are substantially equal to cycle time of desired frequency divided by twice the number of segments. The capacitance of each segment is determined to be substantially equal to the largest envisaged load capacitance (including or preferably differential load capacitance) plus loop-to-loop interconnect capacitance plus active device (say and usually transistor) capacitance of voltage-transition regenerative means and addition to unloaded segments of padding capacitance calculated substantially to match the lumped line capacitance, and pitch/width of differencial transmission-line conductors is calculated using Wheeler's formula constrained by metallization factor involved. Finally a suitable odd number of cross-overs of transmission-line conductors is ascertained to meet cross-talk desiderata and number of transmission line loops specified to cover the area to be serviced and their interconnections, say conveniently at corners of rectangular said regions; and account taken of up to all of interconnect inductance, conduction skin effects, cross-talk, and MOSFET parasitics at least for high frequency applications.

Titel:	Timing circuit cad
Autor/in / Beteiligte Person:	Wood, John
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2007
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 7,203,914 Publication Date: April 10, 2007 Appl. No: 10/497730 Application Filed: December 06, 2002 Assignees: MultiGIG Ltd. (GB) Claim: 1. A method to generate a design for timing circuitry that provides a traveling-wave type timing signal waveform along a path of transmission line nature, comprising: determining a plurality of regions of the timing circuitry, each region being sized such that a signal delay, along the path, between adjoining ones of such regions is below a particular fraction of a target operating frequency; generating a design for each of the determined regions of the timing circuitry such that, for each region individually, that region nominally has particular desired characteristics, the designs for the determined regions constituting an entire design; simulating operation of the entire design; selectively adjusting the design for at least some of the regions based on a result of the simulating step; and repeating the steps of simulating and selectively adjusting as appropriate until the result of the simulating step is a desired result. Claim: 2. The method of claim 1 , wherein the step of determining a plurality of regions includes: for each region, dividing perimeters of each region into a number of segments; approximating lumped transmission line LCR for at least some of the segments; and determining relevant parameters such that time delays over each segment have a particular relationship to a function of the target frequency and the number of segments for the perimeter of that region. Claim: 3. The method of claim 2 , wherein the function of the target frequency and the number of segments for the perimeter of that region is the target frequency divided by twice the number of segments. Claim: 4. The method of claim 3 , wherein the particular relationship is substantial equality. Claim: 5. The method of claim 1 , wherein the timing circuitry includes regenerative means distributed along the path to control voltage transitions in the timing signal waveform; and wherein step the step of determining a plurality of regions includes, for each region, dividing perimeters of each region into segments; and determining a lumped capacitance of each segment to be substantially equal to a worst case load capacitance plus loop-to-loop interconnect capacitance plus active delay capacitance of the regenerative means. Claim: 6. The method of claim 2 , wherein the step of determining a plurality of regions further includes, for unloaded segments, determining a padding capacitance to substantially match the capacitance of the lumped line capacitance. Current U.S. Class: 716/4 Patent References Cited: 6460165 October 2002 Ismail et al. ; 2003/0131329 July 2003 Gonzalez ; 2349524 November 2000 Other References: International Search Report; ref: PCT/GB02/05514, Jan. 29, 2004. cited by other ; Wood, John. et al., “Rotary traveling-wave oscillator arrays: a new clock technology,” IEEE Journal of Solid-State Circuits, Nov. 2001, vol. 36, No. 11, pp. 1654-1665. cited by other ; MultiGiG ltd: Rotary Explorer Vo. 5 User's Guide, 'online! Apr. 28, 2001, pp. 1-33. cited by other Primary Examiner: Dinh, Paul Attorney, Agent or Firm: Diepenbrock, III, Anthony B. ; Dechert LLP

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Timing circuit cad