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A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Titel:	Method of manufacturing semiconductor device with offset sidewall structure
Autor/in / Beteiligte Person:	Ota, Kazunobu ; Sayama, Hirokazu ; Oda, Hidekazu
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2007
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 7,220,637 Publication Date: May 22, 2007 Appl. No: 10/212252 Application Filed: August 06, 2002 Assignees: Renesas Technology Corp. (Tokyo, JP) Claim: 1. A method of manufacturing a semiconductor device comprising the steps of: (a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor; (b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region and forming both a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively; and (c) ion implanting an N-type impurity using at least said first gate electrode of said first NMOS region as part of an implant mask to form a pair of first extension layers in the surface of said semiconductor substrate outside a side surface of said first gate electrode of said first NMOS region, and ion implanting a P-type impurity using at least said second gate electrode of said first PMOS region as part of an implant mask to form a pair of second extension layers in the surface of said semiconductor substrate outside a side surface of said second gate electrode of said first PMOS region, said step (c) including the step of: (c- 1) forming a pair of first ion-implanted layers by ion implantation of said N-type impurity in said first NMOS region and forming a pair of second ion-implanted layers by ion implantation of said P-type impurirty in said first PMOS region, wherein a spacing between said second ion-implanted layers is wider than a spacing between said first ion-implanted layers, said first and second ion-implanted layers grow into said first and second extension layers respectively through heat treatment when forming source and drain layers of both said first NMOS transistor and said first PMOS transistor, and said step (c- 1) includes the steps of: (c- 1 - 1) forming a first offset sidewall with a silicon oxide film on side surface of said first and second gate electrodes; (c- 1 - 2) ion implanting said N-type impurity into said first NMOS region using said first gate electrode and said first offset sidewall as implant masks to form said first ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode; (c- 1 - 3) forming a second offset sidewall on a side surface of said first offset sidewall; and (c- 1 - 4) ion implanting said P-type impurity into said first PMOS region using said second gate electrode and said first and second offset sidewalls as implant masks to form said second ion-implanted layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode. Claim: 2. The method according to claim 1 , wherein said step (a) includes the step of further sectioning said major surface of said semiconductor substrate into a second NMOS region for forming a second NMOS transistor with a higher operating voltage than said first NMOS transistor and a second PMOS region for forming a second PMOS transistor with a higher operating voltage than said first PMOS transistor; and said step (b) includes the step of: selectively forming a second gate insulating film greater in thickness than said first gate insulating film on both said second NMOS region and said second PMOS region, to form a third gate electrode and a fourth gate electrode on said second gate insulating film in said second NMOS region and said second PMOS region, respectively, the method further comprising the steps, performed prior to said step (c), of: forming an offset sidewall on side surfaces of said third and fourth gate electrodes; ion implanting an N-type impurity into said second NMOS region using said third gate electrode and said offset sidewall as implant masks to form a pair of third extension layers in the surface of said semiconductor substrate outside the side surface of said third gate electrode; and ion implanting a P-type impurity into said second PMOS region using said fourth gate electrode and said offset sidewall as implant masks to form a pair of fourth extension layers in the surface of said semiconductor substrate outside the side surface of said fourth gate electrode. Claim: 3. The method according to claim 2 , wherein said step (c- 1 - 1) includes the step of forming a first insulation film on the whole surface of said semiconductor substrate to cover said offset sidewall and forming said first offset sidewall by increasing the thickness of said offset sidewall. Claim: 4. The method according to claim 1 , further comprising the steps of: (d) forming a first sidewall insulating film on a side surface of said second offset sidewall in at least said first NMOS region and said first PMOS region; (e) ion implanting an N-type impurity into at least said first NMOS region using said first gate electrode, said first and second offset sidewalls and said first sidewall insulating film an implant masks, to form first source/drain layers in the surface of said semiconductor substrate outside the side surface of said first gate electrode; (f) forming a second sidewall insulating film on a side surface of said first sidewall insulating film; and (g) ion implanting a P-type impurity into at least said first PMOS region using said second gate electrode, said first and second offset sidewalls and said first and second sidewall insulating films as implant masks, to form second source/drain layers in the surface of said semiconductor substrate outside the side surface of said second gate electrode, said steps (d) and (e) being performed after said step (c), said steps (f) and (g) being performed after said step (e). Claim: 5. The method according to claim 1 , wherein said step (c- 1 - 1) includes the step of forming a first insulating film on the whole surface of said semiconductor substrate and, by selectively removing a first part of said first insulation film on the surface of said semiconductor substrate by anisotropic etching, leaving a second part of said first insulation film on the side surfaces of said first and second gate electrodes to form said first offset sidewall, said step (c- 1 - 3) includes the step of forming a second insulation film on the whole surface of said semiconductor substrate, said second insulation film formed on the side surface of said first offset sidewall forming said second offset sidewall, and said step (c- 1 - 4) includes the step of ion implanting said P-type impurity through said second insulation film and into the surface of said semiconductor substrate with said second offset sidewall formed on a side surface of said first offset sidewall and with said second insulation film formed on the surface of said semiconductor substrate. Current U.S. Class: 438/230 Patent References Cited: 5405791 April 1995 Ahmad et al. ; 6380021 April 2002 Wang et al. ; 6492218 December 2002 Mineji ; 9-167804 June 1997 Other References: H. Sayama, et al. “80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process” IEEE 2000, 4 pages. cited by other ; Pending U.S. Appl. No. 09/796,597, filed Mar. 2, 2001. cited by other Primary Examiner: Crane, Sara Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

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Method of manufacturing semiconductor device with offset sidewall structure