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A source driving circuit includes a shift register, a data latch circuit, a D/A converter, and a sample-and-hold circuit. The shift register generates an n-bit first signal in response to a clock signal and an input/output control signal, wherein n is a positive integer. The data latch circuit samples video data using the first signal to latch the sampled video data, and outputs 3×n digital signals. The D/A converter generates a plurality of analog voltage signals corresponding to the 3×n digital signals using a plurality of gray scale voltages. The sample-and-hold circuit generates 6×n sample-and-hold signals using the analog voltage signals in response to a plurality of switching control signals.

Titel:	Source driving circuit of display device and source driving method thereof
Autor/in / Beteiligte Person:	Choi, Chang-Hwe
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2009
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 7,616,183 Publication Date: November 10, 2009 Appl. No: 11/298913 Application Filed: December 09, 2005 Assignees: Samsung Electronics Co., Ltd. (Suwon-Si, KR) Claim: 1. A source driving circuit of a display device, comprising: a shift register configured to generate an n-bit first signal in response to a clock signal and an input/output control signal; a data latch circuit configured to sample video data using the first signal to latch the sampled video data, and configured to output 3.times.n digital signals; a D/A converter configured to generate a plurality of analog voltage signals corresponding to the 3.times.n digital signals using a plurality of gray scale voltages; and a sample-and-hold circuit configured to generate 6.times.n sample-and-hold signals using the analog voltage signals in response to a plurality of switching control signals, wherein n is a positive integer, wherein the sample-and-hold circuit comprises: a buffer circuit configured to buffer the analog voltage signals; a switching circuit configured to output the buffered signals of the buffer circuit in response to the switching control signals; and a storage circuit configured to store the output signals of the switching circuit, wherein the switching circuit comprises: a plurality of MOS transistors; and a plurality of MOS capacitors respectively coupled between the storage circuit and gates of the MOS transistors. Claim: 2. The source driving circuit of claim 1 , wherein the data latch circuit outputs the 3.times.n digital signals in response to a load signal. Claim: 3. The source driving circuit of claim 1 , wherein the buffer circuit comprises a plurality of voltage followers. Claim: 4. The source driving circuit of claim 1 , wherein the storage circuit comprises a plurality of capacitors. Claim: 5. The source driving circuit of claim 1 , further comprising an output buffer configured to buffer the sample-and-hold signals to select the 3.times.n signals of the 6.times.n sample-and-hold signals, and configured to output the selected sample-and-hold signals as source signals. Claim: 6. The source driving circuit of claim 5 , wherein the output buffer comprises: a buffer circuit configured to buffer the signals; and a selecting circuit configured to select half of the output signals of the buffer circuit. Claim: 7. The source driving circuit of claim 6 , wherein the selecting circuit comprises a plurality of multiplexers configured to receive two signals and select one of the two signals. Claim: 8. The source driving circuit of claim 1 , further comprising a sample-and-hold controller configured to generate the switching control signals in response to a sample-and-hold control signal. Claim: 9. The source driving circuit of claim 1 , further comprising a gray scale voltage generator configured to generate the gray scale voltages. Claim: 10. A display device comprising: a controller configured to generate a plurality of gate control signals, a clock signal, a plurality of input/output control signals, a load signal, and a sample-and-hold control signal; a gate driving circuit configured to generate a plurality of gate signals in response to the gate control signals and configured to supply the gate signals to gate lines of a display panel; and a source driving circuit, wherein the source driving circuit comprises: a shift register configured to generate an n-bit first signal in response to the clock signal and the input/output control signal; a data latch circuit configured to sample video data using the first signal to latch the sampled video data, and configured to output 3.times.n digital signals; a D/A converter configured to generate a plurality of analog voltage signals corresponding to the 3.times.n digital signals using gray scale voltages; and a sample-and-hold circuit configured to generate 6.times.n second signals using the analog voltage signals in response to a plurality of switching control signals, wherein n is a positive integer, wherein the sample-and-hold circuit comprises: a buffer circuit configured to buffer the analog voltage signals; a switching circuit configured to output the buffered signals of the buffer circuit in response to the switching control signals; and a storage circuit configured to store the output signals of the switching circuit wherein the switching circuit comprises: a plurality of MOS transistors; and a plurality of MOS capacitors respectively coupled between the storage circuit and gates of the MOS transistors. Claim: 11. The display device of claim 10 , wherein the source driving circuit further comprises an output buffer configured to buffer the sample-and-hold signals and select the 3.times.n sample-and-hold signals of the 6.times.n sample-and-hold second signals, and output the selected sample-and-hold signals as source signals. Claim: 12. The display device of claim 10 , wherein the data latch circuit outputs the 3.times.n digital signals in response to the load signal. Claim: 13. The display device of claim 10 , wherein the source driving circuit further comprises a sample-and-hold controller configured to generate the switching control signals in response to a sample-and-hold control signal. Claim: 14. The display device of claim 10 , wherein the source driving circuit further comprises a gray scale voltage generator configured to generate the gray scale voltages. Claim: 15. A sample-and-hold circuit comprising: a buffer circuit configured to buffer 3×n analog voltage signals; a switching circuit configured to generate 6×n signals using the buffered signals of the buffer circuit in response to a plurality of switching control signals; and a storage circuit configured to store the output signals of the switching circuit, wherein n is a positive integer, wherein the switching circuit comprises: a plurality of MOS transistors; and a plurality of MOS capacitors respectively coupled between the storage circuit and gates of the MOS transistors. Claim: 16. The sample-and-hold circuit of claim 15 , wherein the buffer circuit comprises a plurality of voltage followers and wherein the storage circuit comprises a plurality of capacitors. Current U.S. Class: 345/100 Patent References Cited: 5192945 March 1993 Kusada ; 5604511 February 1997 Ohi ; 5623279 April 1997 Itakura et al. ; 5900853 May 1999 Shimizu et al. ; 5903250 May 1999 Lee et al. ; 6049321 April 2000 Sasaki ; 6069519 May 2000 Song ; 6522317 February 2003 Satou et al. ; 6538631 March 2003 Kwon ; 6999015 February 2006 Zhang et al. ; 7064695 June 2006 Koo ; 2004/0041601 March 2004 Payne et al. ; 199911249633 September 1999 ; 2000112444 April 2000 ; 20000200069 July 2000 ; 20030150126 May 2003 ; 19920022194 December 1992 ; 20040077016 September 2004 Other References: English Abstract***. cited by other ; English Abstract of Publication No. 1992-22194. cited by other Assistant Examiner: Pham, Viet Primary Examiner: Tran, Henry N Attorney, Agent or Firm: F. Chau & Assoc., LLC

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Source driving circuit of display device and source driving method thereof