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A data processing system and method of isolating a plurality of I/O adapters in the system. The data processing system also comprises a set of processors communicating with the I/O adapters using a PCIe protocol. Each of the I/O adapters has a respective ID. In the preferred embodiment the commands issued by the I/O adapters include a PCIe defined Requestor ID field including one or more of the Requestor IDs of I/O Adapters. The Req IDs can be used as an input to a CAM which provides an index to a TVT to identify a unique and independent system memory space for the I/O adapter.

Titel:	I/O adapter LPAR isolation with assigned memory space
Autor/in / Beteiligte Person:	Gregg, Thomas A.
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2009
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 7,617,340 Publication Date: November 10, 2009 Appl. No: 11/621334 Application Filed: January 09, 2007 Assignees: International Business Machines Corporation (Armonk, NY, US) Claim: 1. A method of isolating a plurality of I/O adapter units of a data processing system, said data processing system comprising a set of processors, content addressable memory (CAM), and a translation validation table (TVT), said method comprising: the processors assigning to each of the I/O adapter units a respective identifier; the I/O adapter units sending memory requests to the set of processors, each request including said respective identifier; the processors indexing in the TVT a memory space requested by said each request based on an index value provided by the CAM in response to the respective identifier; and the processors using the respective identifier as an index into the TVT pointing to translation validation entries (TVE) containing a translation address register (TAR) comprising a base address to identify a unique and independent memory space in system memory associated with the one of I/O adapter units. Claim: 2. The method according to claim 1 , further comprising the step of the processors sending a response packet including the respective identifier for identifying a requesting I/O adapter unit. Claim: 3. The method according to claim 1 , further comprising the step of the set of processors using the respective identifier as an index into said CAM to generate an index value and to use the index value as an index into the TVT to identify one of the I/O adapter units. Claim: 4. The method according to claim 1 further comprising the step of, wherein the set of processors include a plurality of logical partitions, assigning each of the plurality of I/O adapter units, on the basis of its respective identifier, to a different one of said partitions. Claim: 5. The method according to claim 4 , further comprising the step of verifying that the memory space requested by said one of the I/O adapter units is in its assigned logical partition. Claim: 6. The method according to claim 5 , wherein the step of verifying further comprises the step of comparing an address limit value with address bits associated with said one of the I/O adapter units. Claim: 7. The method according to claim 6 , wherein the address bits comprise higher order address bits associated with said one of the I/O adapter units for restricting use of the memory space by said one of the I/O adapter units. Current U.S. Class: 710/62 Patent References Cited: 5497490 March 1996 Harada et al. ; 6002883 December 1999 Goldrian ; 6311255 October 2001 Sadana ; 6523140 February 2003 Arndt et al. ; 6721816 April 2004 Magro et al. ; 7007125 February 2006 Barker et al. ; 7225287 May 2007 Wooten ; 7363404 April 2008 Boyd et al. ; 2002/0152335 October 2002 Holm et al. ; 2002/0194437 December 2002 Kapoor et al. ; 2003/0145136 July 2003 Tierney et al. ; 2003/0172322 September 2003 Kitamorn et al. ; 2003/0236852 December 2003 Fernandes et al. ; 2004/0030712 February 2004 Sano et al. ; 2004/0210817 October 2004 Kapoor et al. ; 2006/0010276 January 2006 Arndt et al. ; 2006/0010355 January 2006 Arndt et al. ; 2006/0064523 March 2006 Moriki et al. ; 2006/0179195 August 2006 Sharma et al. ; 2006/0195675 August 2006 Arndt et al. ; 2007/0136554 June 2007 Biran et al. ; 2007/0168636 July 2007 Hummel et al. ; 2007/0168641 July 2007 Hummel et al. ; 2007/0168644 July 2007 Hummel et al. ; 2008/0147891 June 2008 Gregg ; 2008/0168186 July 2008 Gregg ; 2008/0168207 July 2008 Gregg ; 2008/0168208 July 2008 Gregg Other References: Advanced Micro Devices, PID 34434 Rev. 1.00—Feb. 3, 2006, 'AMD I/O Virtualization Technology (IOMMU) Specification, pp. 1-52. cited by other Assistant Examiner: Nam, Hyun Primary Examiner: Tsai, Henry W. H. Attorney, Agent or Firm: Ortega, Arthur

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I/O adapter LPAR isolation with assigned memory space