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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 7,760,000
- Publication Date: July 20, 2010
- Appl. No: 12/149564
- Application Filed: May 05, 2008
- Assignees: NEC Electronics Corporation (Kawasaki, Kanagawa, JP)
- Claim: 1. A clock generator comprising: a ring oscillator including a plurality of differential circuits coupled together in a series, each differential circuit including a differential input and a differential output, a differential output of one circuit being coupled to a differential input of a next one of said circuits in said plurality of circuits, said plurality of circuits including a first circuit and a last circuit, said a differential output of said last circuit being coupled to a differential input of said first circuit, said plurality of circuits comprising an even numbered subplurality of differential circuits and an odd numbered subplurality of differential circuits alternately coupled with each other in said series, said plurality of differential circuits arranged and configured to produce an odd number of inversions of a signal in one pass through said plurality of differential circuits; and a level converter receiving two input signals, generating an output signal, and providing a characteristic between said output signal and a difference between said two input signals, said characteristic having an odd function being geometrically symmetric with respect to a crossing point of same level between said two input signals, one of said two input signals revealed to said output from one of said differential circuits of said odd numbered subplurality of differential circuits, the other one of said two input signals revealed to said output from one of said differential circuits of said even numbered subplurality of differential circuits.
- Claim: 2. The clock generator according to claim 1 , wherein the ring oscillator includes a differential input pair of lines provided on said input of each delay circuit and a differential output pair of lines provided on said output of each said delay circuit, said differential output pair of lines provided on one circuit being cascadedly coupled to said differential input pair of lines provided on a next one of said circuits in said plurality of circuits.
- Claim: 3. The clock generator according to claim 2 , wherein the one of said two input signals is revealed to one of said output pair of lines provided on said output from one of said differential circuits of said odd numbered subplurality of differential circuits and the other one of said two input signals is revealed to one of said output pair of lines provided on said output from one of said differential circuits of said even numbered subplurality of differential circuits.
- Claim: 4. The clock generator according to claim 3 , wherein the one of said differential circuits of said odd numbered subplurality is sequentially adjacent to the one of said differential circuits of said even numbered subplurality.
- Claim: 5. The clock generator according to claim 2 , wherein a number of said circuits comprising said plurality of differential circuits is an even number.
- Claim: 6. The clock generator according to claim 5 , wherein the differential output pair of lines provided on said output of said last circuit is cross-coupled to the differential input pair of lines provided on said input of said first circuit to arrange and configure to produce an odd number of inversions of a signal in one pass through said plurality of differential circuits.
- Claim: 7. The clock generator according to claim 6 , wherein the one of said two input signals is revealed to its one of said differential output pair of lines provided on said output of said last circuit and the other one of said two input signals is revealed to its other one of said differential output pair of lines provided on said input of said first circuit.
- Claim: 8. The clock generator according to claim 2 , wherein a number of said circuits comprising said plurality of differential circuits is an odd number.
- Claim: 9. The clock generator according to claim 8 , wherein the differential output pair of lines provided on said output of said last circuit is cascadedly coupled to the differential input pair of lines provided on said input of said first circuit to arrange and configure to produce an odd number of inversions of a signal in one pass through said plurality of differential circuits.
- Claim: 10. The clock generator according to claim 9 , wherein the one of said two input signals is revealed to its one of said differential output pair of lines provided on said output of said last circuit and the other one of said two input signals is revealed to its one of said differential output pair of lines provided on said input of said first circuit.
- Claim: 11. A clock generator comprising: a ring oscillator including a plurality of inverting delay circuits coupled together in a cascaded series, each delay circuit including an input and an output, said output of one delay circuit coupled to said input of a next sequential one of said delay circuits, said plurality of delay circuits comprising a cascaded series, said cascaded series including a first delay circuit and a last delay circuit, said last delay circuit having its output coupled to said input of said first delay circuit, said cascaded series of delay circuits comprising an odd numbered subplurality of delay circuits and an even numbered subplurality of delay circuits alternately coupled in sequence to each other; and a level converter receiving two input signals, generating an output signal and providing a characteristic between said output signal and a difference between said two input signals, said characteristic having an odd function being geometrically symmetric with respect to a crossing point of same level between said two input signals, one of said two input signals revealed to said output from one of said delay circuits of said odd numbered subplurality, the other one of said two input signals revealed to said output from one of said delay circuits of said even numbered subplurality.
- Claim: 12. A clock generator comprising: a ring oscillator including a plurality of differential circuits alternating between odd numbered differential circuits and even numbered differential circuits coupled in a series, each differential circuit including a differential output transferring a signal to a differential input of a next differential circuit; and a level converter receiving two input signals, generating an output signal and providing a characteristic between said output signal and a difference between said two input signals, the characteristic having an odd function being geometrically symmetric with respect to a same-level crossing point between said two input signals, one of the two input signals revealed to the output from one of the differential circuits of the odd numbered differential circuits, the other one of the two input signals revealed to the output from one of the differential circuits of the even numbered differential circuits.
- Claim: 13. The clock generator according to claim 12 , wherein a differential output of a last one of the differential circuits is transferred to a differential input of a first one of the plurality of differential circuits arranged in the series.
- Claim: 14. The clock generator according to claim 12 , wherein the plurality of differential circuits provides an odd number of inversions of a signal in one pass through the plurality of differential circuits arranged in the series.
- Claim: 15. The clock generator according to claim 12 , wherein the one of the differential circuits of the odd numbered differential circuits is sequentially adjacent to the one of the differential circuits of the even numbered differential circuits.
- Claim: 16. The clock generator according to claim 12 , wherein a number of the circuits comprising the plurality of differential circuits is greater than two.
- Claim: 17. The clock generator according to claim 12 , wherein the ring oscillator comprises a differential input pair of lines provided on said input of each delay circuit and a differential output pair of lines provided on said output of each said delay circuit, the differential output pair of lines provided on one circuit being cascadedly coupled to said differential input pair of lines provided on a next one of said circuits in said plurality of circuits.
- Claim: 18. The clock generator according to claim 17 , wherein the one of said two input signals is revealed to one of said output pair of lines provided on said output from one of said differential circuits of the odd numbered differential circuits and the other one of the two input signals is revealed to one of the output pair of lines provided on said output from one of said differential circuits of even numbered differential circuits.
- Claim: 19. The clock generator according to claim 17 , wherein the differential output pair of lines provided on the output of a last one of the differential circuits is cross-coupled to the differential input pair of lines provided on the input of the first circuit to arrange and configure to produce an odd number of inversions of a signal in one pass through the plurality of differential circuits.
- Claim: 20. The clock generator according to claim 17 , wherein one of the two input signals is revealed to one of the differential output pair of lines provided on the output of a last differential circuit and the other one of the two input signals is revealed to the other one of the differential output pair of lines provided on the input of the first one of the differential circuits.
- Current U.S. Class: 327/293
- Patent References Cited: 5180994 January 1993 Martin et al. ; 5548251 August 1996 Chou et al. ; 6271732 August 2001 Herzel ; 6388492 May 2002 Miura et al. ; 6775217 August 2004 Kato et al. ; 07-007397 January 1995 ; 10-335991 December 1998 ; 2000-156629 June 2000 ; 2002-141785 May 2002 ; 2006-294131 October 2006 ; WO2006/030905 March 2006
- Other References: Japenese Office Action dated Apr. 7, 2009 with a partial English-Language translation. cited by other
- Assistant Examiner: Nguyen, Hai L
- Primary Examiner: Donovan, Lincoln
- Attorney, Agent or Firm: McGinn IP Law Group, PLLC
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