Einzeltreffer — DigiBib

A thin, small outline IC leadframe plastic package to be used to assemble high performance, high speed semiconductor memory IC devices such as dynamic random access memories (DRAM) having a high data transfer rate in the range of 1 GigaHertz. The package leadframe is electrically interconnected to the IC device input-output pads by either electrically conductive (e.g. solder) bumps that are flip-chip bonded to the IC device or by of an interposer. The interposer contains integral curled micro-spring contacts at opposite ends of conductive fan out traces. The interposer is attached to the leadframe bonding pads by way of tape automated bonding, soldering, or adhesive bonding. The leadframe that is interconnected to the IC device by the aforementioned flip-chip bumps or the interposer is encapsulated and trimmed to form either gull-wing style perimeter leads as a standard thin small outline package (TSOP) or wrap around leads as a micro-leadframe (MLF) package.

Titel:	Encapsulated leadframe semiconductor package for random access memory integrated circuits
Autor/in / Beteiligte Person:	Koh, Wei H. ; Kong, Fred ; Chen, David
Link:	View record in USPTO Patent Grants (Volltext)
Veröffentlichung:	2010
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Grants Sprachen: English Patent Number: 7,781,873 Publication Date: August 24, 2010 Appl. No: 10/424096 Application Filed: April 28, 2003 Assignees: Kingston Technology Corporation (Fountain Valley, CA, US) Claim: 1. A semiconductor leadframe package comprising an encapsulated body, said encapsulated body including therewithin an integrated circuit chip, a plurality of bonding pads attached to the integrated circuit chip, a set of conductive traces lying on a surface of said integrated circuit chip and connected to respective ones of the bonding pads, said conductive traces fanning outwardly from respective ones of said plurality of bonding pads over said integrated circuit chip, a leadframe overhanging the set of conductive traces and said integrated circuit chip within said encapsulated body and having a plurality of leads extending to a location at the exterior of said body, and electrically conductive bumps connected between the set of conductive traces on the surface of said integrated circuit chip and the leadframe at a location where said leadframe overhangs said conductive traces and said integrated circuit chip within said encapsulated body by which each of said plurality of leads of the leadframe is electrically connected directly to a respective one of the plurality of bonding pads by way of an electrical series connection of a corresponding conductive trace of said set of conductive traces and an electrically conductive bump and without any wire bonding connections wherein said encapsulated body includes a redistribution layer located on a surface of said integrated circuit chip, said redistribution layer having formed thereon said set of conductive traces and an array of trace terminal bump pads communicating with said set of traces, said trace terminal bump pads establishing terminals at the location where said leadframe overhangs said conductive traces and said integrated circuit chip at which said electrically conductive bumps are located so as to be connected between respective ones of said set of conductive traces and said leadframe. Claim: 2. The semiconductor leadframe package recited in claim 1 , wherein said electrically conductive bumps are flip-chip bonded to the surface of said integrated circuit chip during the manufacture of said chip. Claim: 3. The semiconductor leadframe package recited in claim 1 , wherein said electrically conductive bumps are fabricated from solder. Claim: 4. The semiconductor leadframe package recited in claim 3 , wherein said electrically conductive solder bumps are connected to said leadframe within said encapsulated body by means of oven reflow. Claim: 5. The semiconductor leadframe package recited in claim 3 , wherein said electrically conductive solder bumps are connected to said leadframe within said encapsulated body by means of compression and heat cure. Claim: 6. The semiconductor leadframe package recited in claim 1 , wherein said electrically conductive bumps are fabricated from an electrically conductive material selected from a set of electrically conductive materials comprising gold, nickel/gold and conductive polymer. Claim: 7. The semiconductor leadframe package recited in claim 1 , wherein said leadframe extending to the exterior of said encapsulated body includes tips that are bent into a gull-wing shape, whereby said package is a thin small outline package. Claim: 8. The semiconductor leadframe package recited in claim 1 , wherein said leadframe extending to the exterior of said encapsulated body includes tips that are wrapped under said body, whereby said package is a micro-leadframe package. Claim: 9. The semiconductor leadframe package recited in claim 1 , wherein said encapsulated body includes a plurality of said electrically conductive bumps by which to connect each trace of said set of conductive traces to said leadframe within said body. Claim: 10. A semiconductor leadframe package comprising an encapsulated body, said encapsulated body including therewithin an integrated circuit chip, a plurality of bonding pads attached to the integrated circuit chip, a set of conductive traces connected to and fanning outwardly from respective ones of the bonding pads, a leadframe overhanging and being electrically connected to the set of conductive traces within said body and extending to a location at the exterior of said body, an interposer comprising an insulating substrate located between said leadframe and said set of conductive traces such that said leadframe lies on a first surface of said insulating substrate and said set of conductive traces lie on an opposite surface of said insulating substrate, first contacts connected to each of said set of conductive traces to connect first ends of respective ones of the set of conductive traces directly to corresponding ones of the plurality of bonding pads without wire bonding connections, and second contacts connected to each of said set of conductive traces to connect opposite ends of the set of conductive traces to the leadframe wherein the second contacts connected to each of said set of conductive traces extend beyond the insulating substrate on which said set of conductive traces are formed by means of which respective ones of said set of conductive traces are connected directly to said leadframe without intermediate bonding connections. Claim: 11. The semiconductor leadframe package recited in claim 10 , wherein the substrate of said interposer is manufactured from a flexible material. Claim: 12. The semiconductor leadframe package recited in claim 10 , wherein said first and second contacts are flexible microsprings having a spring memory. Claim: 13. The semiconductor leadframe package recited in claim 12 , wherein said first and second microspring contacts are curved. Claim: 14. The semiconductor leadframe package recited in claim 13 , wherein the first and second microspring contacts are curved in opposite directions relative to one another. Claim: 15. The semiconductor leadframe package recited in claim 10 , wherein said set of conductive traces are disposed within said encapsulated body so as to lie between the insulating substrate of said interposer and said plurality of bonding pads. Claim: 16. A semiconductor leadframe package comprising an encapsulated body, said encapsulated body including therewithin an integrated circuit chip, a plurality of bonding pads attached to the integrated circuit chip, an insulating substrate, a leadframe located at one side of said insulating substrate, a set of conductive traces located at the opposite side of said insulating substrate and fanning thereacross, first contacts comprising first curved microsprings located at first ends of respective ones of said set of conductive traces for electrical connection to said leadframe at the interior of the encapsulated body and second contacts comprising second curved microsprings located at opposite ends of respective ones of said set of conductive traces for electrical connection to corresponding ones of the plurality of bonding pads, whereby said leadframe is connected to said plurality of bonding pads by way of said set of conductive traces and without any wire bonding connections, said leadframe overhanging said insulating substrate and the set of conductive traces located at the opposite side of said insulating substrate at the interior of the encapsulated body and said leadframe extending to the exterior of the encapsulated body. Current U.S. Class: 257/673 Patent References Cited: 5083191 January 1992 Ueda ; 5239198 August 1993 Lin et al. ; 5250841 October 1993 Sloan et al. ; H1267 December 1993 Boyd ; 5367253 November 1994 Wood et al. ; 5369545 November 1994 Bhattacharyya et al. ; 5437915 August 1995 Nishimura et al. ; 5442231 August 1995 Miyamoto et al. ; 5471369 November 1995 Honda et al. ; 5594626 January 1997 Rostoker et al. ; 5677567 October 1997 Ma et al. ; 5763952 June 1998 Lynch et al. ; 5777386 July 1998 Higashi et al. ; 5790378 August 1998 Chillara ; 5917242 June 1999 Ball ; 6002167 December 1999 Hatano et al. ; 6087718 July 2000 Cho ; 6093958 July 2000 Inaba ; 6169328 January 2001 Mitchell et al. ; 6211576 April 2001 Shimizu et al. ; 6229202 May 2001 Corisis ; 6232213 May 2001 King et al. ; 6337522 January 2002 Kang et al. ; 6342727 January 2002 Fujimori ; 6440772 August 2002 Smith ; 6498389 December 2002 Kim ; 6640415 November 2003 Eslamy et al. ; 6724074 April 2004 Song et al. ; 2003/0148108 August 2003 Pierce ; 2003/0218237 November 2003 Hall et al. ; 2004/0150082 August 2004 Kajiwara et al. Primary Examiner: Nadav, Ori Attorney, Agent or Firm: Fischer, Morland C.

Klicken Sie ein Format an und speichern Sie dann die Daten oder geben Sie eine Empfänger-Adresse ein und lassen Sie sich per Email zusenden.

BibTeX Citavi, JabRef, u.a.
(Literaturverwaltung)

PDF kein Volltext!
(Merkzettel, Notizen)

RIS Endnote, Citavi u.a.
(Literaturverwaltung)

MODS
(XML zur Weiterverarbeitung)

oder

Wählen Sie das für Sie passende Zitationsformat und kopieren Sie es dann in die Zwischenablage, lassen es sich per Mail zusenden oder speichern es als PDF-Datei.

Gewünschter Zitations-Stil:

oder

Bitte prüfen Sie, ob die Zitation formal korrekt ist, bevor Sie sie in einer Arbeit verwenden. Benutzen Sie gegebenenfalls den "Exportieren"-Dialog, wenn Sie ein Literaturverwaltungsprogramm verwenden und die Zitat-Angaben selbst formatieren wollen.

Encapsulated leadframe semiconductor package for random access memory integrated circuits