| Sonstiges: |
- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 7,809,275
- Publication Date: October 05, 2010
- Appl. No: 11/073452
- Application Filed: March 07, 2005
- Assignees: Finisar Corporation (Sunnyvale, CA, US)
- Claim: 1. A transceiver module, comprising: a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate less than about 10 Gb/s, and wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is transmitted to or received from the host.
- Claim: 2. The transceiver as recited in claim 1 , wherein the bypass circuitry is configured to permit at least one of the serial electrical data streams to bypass corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate of about 8.5 Gb/s.
- Claim: 3. The transceiver as recited in claim 1 , wherein the transceiver is compatible with the Fibre Channel protocol.
- Claim: 4. The transceiver as recited in claim 1 , wherein the transceiver is substantially compliant with the XFP MSA.
- Claim: 5. The transceiver as recited in claim 1 , wherein the bypass circuitry is configured so that for a data rate less than about 10 Gb/s: the first serial electrical data stream bypasses the receiver eye opener circuitry; and the second serial electrical data stream bypasses the transmitter eye opener circuitry.
- Claim: 6. The transceiver as recited in claim 1 , wherein the bypass circuitry comprises first and second portions, the first portion corresponding to the transmitter eye opener circuitry and the second portion corresponding to the receiver eye opener circuitry.
- Claim: 7. The transceiver as recited in claim 1 , wherein the receiver eye opener circuitry and transmitter eye opener circuitry each comprise a respective CDR, multiplexer, and retimer arranged in series.
- Claim: 8. The transceiver as recited in claim 1 , wherein operation of the receiver eye opener circuitry and transmitter eye opener circuitry is responsive to a detected data rate.
- Claim: 9. The transceiver as recited in claim 1 , wherein bypass of the at least one serial electrical data stream occurs automatically.
- Claim: 10. The transceiver as recited in claim 1 , further comprising diagnostics circuitry configured to provide information concerning the performance of at least one of the ROSA; and, the TOSA.
- Claim: 11. A transceiver module, comprising: a plurality of components that are substantially compliant with the XFP MSA and are compatible for use in a Fibre Channel system, the plurality of components including: a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream at the first output is delivered to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate of about 8.5 Gb/s, wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is delivered to or received from the host.
- Claim: 12. The transceiver module as recited in claim 11 , wherein the bypass circuitry is configured to operate in connection with one of: an LOL signal; an LOS signal; and, a bypass signal.
- Claim: 13. The transceiver module as recited in claim 11 , wherein the bypass circuitry is configured to permit at least one of the serial electrical data streams to bypass corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate that falls within a predetermined range of bypass data rates.
- Claim: 14. The transceiver module as recited in claim 11 , further comprising bypass control circuitry in communication with the bypass circuitry and configured to receive and transmit signals concerning operation of the bypass circuitry.
- Claim: 15. The transceiver module as recited in claim 14 , wherein the bypass control circuitry is configured for at least one of: manual control; and, automatic operation.
- Claim: 16. A transceiver module, comprising: a TOSA; a ROSA; receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host; transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and bypass circuitry configured to enable at least one of the serial electrical data streams to automatically bypass corresponding eye opener circuitry if the corresponding eye opener circuitry is not locked onto that serial electrical data stream, wherein the corresponding eye opener circuitry is configured to lock onto data streams having a data rate of less than about 8.5 Gb/s.
- Claim: 17. The transceiver module as recited in claim 16 , wherein an ability of the eye opener circuitry to lock onto a serial electrical data stream is a function of a data rate associated with that data stream.
- Claim: 18. The transceiver module as recited in claim 16 , wherein automatic bypass of corresponding eye opener circuitry occurs based upon generation of a loss of lock (LOL) signal by the corresponding eye opener circuitry.
- Claim: 19. The transceiver module as recited in claim 16 , wherein the transceiver module is protocol agnostic.
- Current U.S. Class: 398/135
- Patent References Cited: 4359553 November 1982 Edwards ; 4378451 March 1983 Edwards ; 4489477 December 1984 Chik et al. ; 4687924 August 1987 Galvin et al. ; 4734914 March 1988 Yoshikawa ; 4747091 May 1988 Doi ; 4809286 February 1989 Kollanyi et al. ; 4916707 April 1990 Rosenkranz ; 4932038 June 1990 Windus ; 5019769 May 1991 Levinson ; 5039194 August 1991 Block et al. ; 5041491 August 1991 Turke et al. ; 5268949 December 1993 Watanabe et al. ; 5287375 February 1994 Fujimoto ; 5334826 August 1994 Sato et al. ; 5383208 January 1995 Queniat et al. ; 5392273 February 1995 Masaki et al. ; 5396059 March 1995 Yeates ; 5448629 September 1995 Bosch et al. ; 5495358 February 1996 Bartig et al. ; 5516563 May 1996 Schumann et al. ; 5557437 September 1996 Sakai et al. ; 5574435 November 1996 Mochizuki ; 5576877 November 1996 Aulet et al. ; 5586123 December 1996 Baker ; 5594748 January 1997 Jabr ; 5604758 February 1997 AuYeung et al. ; 5673282 September 1997 Wurst ; 5706277 January 1998 Klink ; 5748672 May 1998 Smith et al. ; 5761216 June 1998 Sotome et al. ; 5787114 July 1998 Ramamurthy et al. ; 5801866 September 1998 Chan et al. ; 5802073 September 1998 Platt ; 5812572 September 1998 King et al. ; 5854704 December 1998 Grandpierre ; 5920414 July 1999 Miyachi et al. ; 5926303 July 1999 Giebel et al. ; 5953690 September 1999 Lemon et al. ; 5956168 September 1999 Levinson et al. ; 5966395 October 1999 Ikeda ; 5978417 November 1999 Baker et al. ; 5999294 December 1999 Petsko ; 6049413 April 2000 Taylor ; 6055252 April 2000 Zhang ; 6064501 May 2000 Roberts et al. ; 6075634 June 2000 Casper et al. ; 6157022 December 2000 Maeda et al. ; 6160647 December 2000 Gilliland et al. ; 6175434 January 2001 Feng ; 6188059 February 2001 Nishiyama et al. ; 6198558 March 2001 Graves et al. ; 6205505 March 2001 Jau et al. ; 6215565 April 2001 Davis et al. ; 6222660 April 2001 Traa ; 6229788 May 2001 Graves et al. ; 6252692 June 2001 Roberts ; 6256127 July 2001 Taylor ; 6272154 August 2001 Bala et al. ; 6292497 September 2001 Nakano ; 6313459 November 2001 Hoffe et al. ; 6317232 November 2001 Fee et al. ; 6384948 May 2002 Williams et al. ; 6423963 July 2002 Wu ; 6466886 October 2002 Marmur ; 6469782 October 2002 Schaepperle ; 6473224 October 2002 Dugan et al. ; 6476949 November 2002 Loh et al. ; 6512617 January 2003 Tanji et al. ; 6519255 February 2003 Graves ; 6526076 February 2003 Cham et al. ; 6538783 March 2003 Stephens ; 6570149 May 2003 Maruyama et al. ; 6594050 July 2003 Jannson et al. ; 6631144 October 2003 Johansen ; 6631146 October 2003 Pontis et al. ; 6643472 November 2003 Sakamoto et al. ; 6661836 December 2003 Dalal et al. ; 6661973 December 2003 Huber et al. ; 6665498 December 2003 Jiang et al. ; 6694462 February 2004 Reis et al. ; 6712527 March 2004 Chan et al. ; 6748181 June 2004 Miki et al. ; 6765445 July 2004 Perrott et al. ; 6829436 December 2004 Koh et al. ; 6832052 December 2004 Marmur ; 6909848 June 2005 Kim et al. ; 6937949 August 2005 Fishman et al. ; 6941077 September 2005 Aronson et al. ; 6944404 September 2005 Lange et al. ; 6952531 October 2005 Aronson et al. ; 6956847 October 2005 Heston et al. ; 6977517 December 2005 Miao et al. ; 7010030 March 2006 Vaidyanathan ; 7019548 March 2006 Miao et al. ; 7020567 March 2006 Fishman et al. ; 7024059 April 2006 Kurchuk ; 7031615 April 2006 Gentile ; 7058310 June 2006 Aronson et al. ; 7062164 June 2006 Ames et al. ; 7099382 August 2006 Aronson et al. ; 7110668 September 2006 Gerstel et al. ; 7155127 December 2006 Akimoto et al. ; 7245638 July 2007 Agazzi ; 7308060 December 2007 Wall et al. ; 7437079 October 2008 Hofmeister ; 7477847 January 2009 Hofmeister et al. ; 2001/0046242 November 2001 Kawakami et al. ; 2001/0046243 November 2001 Schie ; 2002/0021468 February 2002 Kato et al. ; 2002/0027688 March 2002 Stephenson ; 2002/0034222 March 2002 Buchwald et al. ; 2002/0060824 May 2002 Liou et al. ; 2002/0075981 June 2002 Tang et al. ; 2002/0080447 June 2002 Fells et al. ; 2002/0097468 July 2002 Mecherle et al. ; 2002/0097682 July 2002 Enam et al. ; 2002/0101641 August 2002 Kurchuk ; 2002/0105982 August 2002 Chin et al. ; 2002/0110157 August 2002 Jorgenson et al. ; 2002/0114061 August 2002 Naito et al. ; 2002/0129379 September 2002 Levinson et al. ; 2002/0131132 September 2002 Tanaka et al. ; 2002/0149812 October 2002 Hong et al. ; 2002/0149821 October 2002 Aronson et al. ; 2002/0163960 November 2002 Blodgett et al. ; 2002/0176518 November 2002 Xu ; 2002/0181519 December 2002 Vilhelmsson et al. ; 2002/0181573 December 2002 Dohmen et al. ; 2002/0181894 December 2002 Gilliand et al. ; 2003/0002108 January 2003 Ames et al. ; 2003/0011847 January 2003 Dai et al. ; 2003/0039207 February 2003 Maeda et al. ; 2003/0053170 March 2003 Levinson et al. ; 2003/0110509 June 2003 Levinson et al. ; 2003/0113118 June 2003 Bartur ; 2003/0169790 September 2003 Chieng et al. ; 2003/0210917 November 2003 Stewart et al. ; 2003/0219085 November 2003 Endres et al. ; 2004/0033079 February 2004 Sheth et al. ; 2004/0052520 March 2004 Halgren et al. ; 2004/0076113 April 2004 Aronson et al. ; 2004/0076114 April 2004 Miriello ; 2004/0076119 April 2004 Aronson et al. ; 2004/0091028 May 2004 Aronson et al. ; 2004/0120720 June 2004 Chang et al. ; 2004/0153913 August 2004 Fishman et al. ; 2004/0202210 October 2004 Thornton ; 2004/0240886 December 2004 Aronson et al. ; 2004/0253003 December 2004 Farmer et al. ; 2005/0031352 February 2005 Light et al. ; 2005/0058455 March 2005 Hosking et al. ; 2005/0111845 May 2005 Nelson et al. ; 2005/0213982 September 2005 Weber ; 2005/0281193 December 2005 Hofmeister et al. ; 2007/0031153 February 2007 Aronson et al. ; 2006220581 October 2008 ; 10065034 August 2001 ; 10392928.2 June 2006 ; 10392928.2 October 2009 ; 0437161 June 1996 ; 0745868 April 2002 ; 1360782 November 2003 ; 1503232 July 2004 ; 1471671 December 2004 ; 2406988 April 2005 ; 0500397.5 June 2005 ; 58140175 August 1983 ; 62124576 June 1987 ; 62235975 October 1987 ; 62281485 December 1987 ; 402102589 April 1990 ; 404023373 January 1992 ; 06209209 July 1994 ; 09162811 June 1997 ; 11-275016 August 1999 ; 2004135106 April 2004 ; 555297 September 2003 ; 224406 November 2004 ; WO 98/00893 January 1998 ; WO 98/00943 August 1998 ; WO 02/063800 August 2002 ; 02003226 October 2002 ; PCT 03761335.3 December 2003 ; WO/2004/098100 November 2004 ; 2005006575 January 2005 ; WO 2006096714 August 2007
- Other References: “Application Note: T2525/26/27”, copyright 2003 by Atmel Corporation. cited by other ; “IR Receiver ASSP: T2525”, copyright 2003 by Atmel Corporation. cited by other ; “IR Receiver for Data Communication: U2538B”, copyright 2003 by Atmel Corporation. cited by other ; “Low-Voltage Highly Selective IR Receiver IC: T2527”, copyright 2002 by Atmel Corporation. cited by other ; Finisar Corp., “App. Note AN-2025: Using the Finisar GBIC I2C Test Diagnostics Port,” 1998. cited by other ; Hausdorf, Reiner, “Mobile Transceiver Measurements with Radiocommunication Service Monitor CMS,” News from Rohde & Schwarz, 127, IV, 1989, pp. 4-7. cited by other ; Kaminishi, K. et al., Si Bipolar 3.3V Transmitter/Receiver IC Chip Set for 1Gb/s 12-Channel Parallel Optical Interconnects, IEEE International Solid-State Circuits Conference, ISSCC, Digest of Technical Papers, 1999 Paper WP 22.1. cited by other ; Maeda, Noriyuki “Notification of Reason(s) for Refusal,” Japanese Patent Application No. JP2002-563630, Nakamura, M. et al., Jul. 13, 2005. cited by other ; Manchester Encoding [retrieved Nov. 12, 2003 from the Internet] http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/man.html. cited by other ; Optiport SFF BiDi-Transceiver 100 Mbit/s, 1310 nm Tx/1550 nm Rx, Infineon Technologies, Jun. 22, 2004, pp. 1-14. cited by other ; Webopedia.com: 12C [retrieved Nov. 11, 2003 from the Internet] http://www.webopedia.com/Term/I/12C.html. cited by other ; Webopedia.com: MAC Address [retrieved Oct. 15, 2003 from the Internet] http://www.webopedia.com/TERM/M/MAC—address.html. cited by other ; Webopedia.com: Public-Key Encryption [retrieved Oct. 15, 2003 from the Internet] http://www.webopedia.com/TERM/p/public—key—cryptography.html. cited by other ; Webopedia: The 7 Layers of the OSI Model [retrieved Oct. 15, 2003 from the Internet] http://webopedia.internet.com/quick—ref/OSI—Layers.asp. cited by other ; Yi Cai et al., “Jitter testing for gigabit serial communication transceivers,” Jan.-Feb. 2002, IEEE Design and Test of Computers, vol. 19, Issue 1, pp. 66-74. cited by other ; U.S. Appl. No. 10/420,027, Jan. 25, 2006, Office Action. cited by other ; U.S. Appl. No. 10/420,027, Sep. 7, 2006, Office Action. cited by other ; U.S. Appl. No. 10/420,027, May 16, 2007, Office Action. cited by other ; U.S. Appl. No. 10/629,725, Oct. 17, 2005, Office Action. cited by other ; U.S. Appl. No. 10/297,725, Apr. 11, 2006, Notice of Allowance. cited by other ; U.S. Appl. No. 10/629,301, Aug. 9, 2007, Office Action. cited by other ; U.S. Appl. No. 10/629,302, Jun. 14, 2007, Office Action. cited by other ; U.S. Appl. No. 10/629,228, Jan. 24, 2006, Office Action. cited by other ; U.S. Appl. No. 10/629,228, Sep. 1, 2006, Office Action. cited by other ; U.S. Appl. No. 10/629,228, May 24, 2007, Office Action. cited by other ; U.S. Appl. No. 10/697,395, Jan. 24, 2006, Office Action. cited by other ; U.S. Appl. No. 10/697,395, Sep. 27, 2006, Office Action. cited by other ; U.S. Appl. No. 10/697,395, May 9, 2007, Office Action. cited by other ; U.S. Appl. No. 10/697,395, Nov. 15, 2007, Office Action. cited by other ; U.S. Appl. No. 10/884,334, Jun. 12, 2007, Office Action. cited by other ; Green, Michael, et al., “Mixing it up with OC-192 CMOS Transceivers”, CommsDesign, An EE Times Community, 8 pgs, May 3, 2006, available at: http://www.commsdesign.com/main/2000/12/0012feat6.htm. cited by other ; Dallas Semiconductor, “HFTA-01.0: 2.5Gbps SDH/SONET Fiber Optic Chipset,” 4 pages Oct. 10, 2000, available at: http://www.maxim-ic.com/appnotes.cfm/appnote—number/713/1n/en. cited by other ; Dallas Semiconductor, “MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier,” 2 pages, Mar. 30, 2003, available at: http://www.maxim-ic.com/quick—view2.cfrn/qv—pk/3705. cited by other ; Huiqing Zhong and Stephen I. Long, “Monothic Clock and Data Recovery Chip for 10GB/S Fiber Communications Systems,” 4 pages 1997-98. cited by other ; GIGA an Intel Company, “2.5 Gbit/s Clock and Data Recovery GD16546B,” 9 pages, Jul. 31, 2001. cited by other ; XFP MSA Group, Ultra Small, 10-Gigabit Module Slashes Cost, Power and Footprint of Telecommunications and Datacommunications Equipment, Press Release, Irvine, California, Mar. 4, 2002. [World Wide Web page]. Available: www.xfpmsa.org/cgi-bin/pressrelease1.cgi. cited by other ; XFP MSA Group New Module to Slash Cost, Power and Size of Telecommunications and Data Communications Equipment, Press Release, Costa Mesa, California, Jul. 22, 2002. [World Wide Web page]. Available: www.xfpmsa.org/cgi-bin/pressrelease3.cgi. cited by other ; Finisar XFP Achieves 300 m Transmission on Legacy Multlimode Fiber, Finisar News Release, Sunnyvale, California, Sep. 17, 2003. [World Wide Web page]. Available: http://investor.finisar.com/ReleaseDetail. cited by other ; XFP MSA Group, About the 10 Gigabit Small Form Factor Pluggable (XFP) Multi Source Agreement (MSA) Group. Feb. 11, 2004. [World Wide Web page]. Available: www.xfpmsa.org/cgi-bin/home.cgi. cited by other ; LXT16706/16707 SerDes Chipset, Intel Products, www.intel.com/design/network/products/optical/phys/1xt16706.htm, Apr. 19, 2002. cited by other ; LXT35401 XAUI-to-Quad 3.2G Transceiver, Intel Products, www.intel.com/design/network/products/optical/phys/lxt35401.htm, Apr. 19, 2002. cited by other ; Texas Instruments User's Guide, TLK2201 Sedes EVM Kit Setup and Usage, Mixed Signal DSP Solutions, Jul. 2000. cited by other ; Texas Instruments User's Guide, TLK1501 Serdes EVM Kit Setup and Usage, Mixed Signal Products, Jun. 2000. cited by other ; National Semiconductor DS92LV16 Design Guide, Serializing Made Simple, Feb. 2002. cited by other ; Vaishali Semiconductor, Fibre Channel Transceiver, VN16117, MDSN-0002-02, Aug. 9, 2001. cited by other ; Fairchild Semiconductor, Application Note 77, CMOS, the Ideal Logic Family, Jan. 1983. cited by other ; Analog Target Specification, Annex 48B, Published by IEEE New York, May 2001, pp. 6-14. cited by other ; A. Ghiasi, “‘XFP’ The Module Based 10Gig Universal Serial Interconnect ‘XFI’”, presentation material, Apr. 8, 2002. cited by other ; Hawthorne: “850nm Proton VCSEL Reliability Study” Technical Publications and Application Notes, Advances Optical Components (Finisar Corp), Issue 2, Sep. 2001, pp. 1-7, Richardson, TX. cited by other ; Mecherle G S et al: “Considerations for Accelerated Laser Diode Life Testing” Proceedings of the Spie, Spie, Bellingham, VA, vol. 717, 1986, pp. 53-62. cited by other ; Tebbi O et al: “Comparitive study of acclerated testing models, applications in mechanics” 2001 IEEE International Conference on Systems Man and Cybernetics SMC 2001. Tucson, AZ Oct. 7-10, 2001, IEEE International Conference on Systems, Man and Cybernetics, New York, NY: IEEE, US, vol. 1 of 5 Oct. 7, 2001 pp. 2099-2104. cited by other ; J.D. Barry et al.: Thermally Accelerated Life Testing of Single Mode, Double-Heterostructure, AlGaAs Laser Diodes Operated Pulsed at 50 mW Peak Power IEEE Journal of Quantum Electronics, vol. 21, No. 4 Dec. 25, 1984 pp. 365-376. cited by other ; U.S. Appl. No. 11/118,172, Mar. 25, 2008, Office Action. cited by other ; U.S. Appl. No. 11/118,172, Sep. 4, 2008, Office Action. cited by other ; U.S. Appl. No. 10/629,302, Jan. 25, 2008, Restriction Requirement. cited by other ; U.S. Appl. No. 10/629,302, May 2, 2008, Office Action. cited by other ; U.S. Appl. No. 10/629,301, Apr. 1, 2008, Office Action. cited by other ; U.S. Appl. No. 10/629,301, filed Nov. 26, 2008, Office Action. cited by other ; U.S. Appl. No. 10/884,334, Jul. 10, 2008, Office Action. cited by other ; U.S. Appl. No. 10/626,965, Jan. 24, 2007, Office Action. cited by other ; U.S. Appl. No. 10/626,965, Aug. 9, 2007, Office Action. cited by other ; U.S. Appl. No. 10/420,027, Dec. 12, 2007, Office Action. cited by other ; U.S. Appl. No. 10/629,228, Jan. 3, 2008, Office Action. cited by other ; U.S. Appl. No. 10/626,965, Mar. 18, 2008, Office Action. cited by other ; U.S. Appl. No. 10/697,395, May 30, 2008, Office Action. cited by other ; U.S. Appl. No. 10/420,027, Jun. 25, 2008, Office Action. cited by other ; U.S. Appl. No. 10/884,334, Jan. 31, 2008, Office Action. cited by other ; U.S. Appl. No. 10/629,302, Nov. 17, 2008, Office Action. cited by other ; U.S. Appl. No. 10/884,334, Jan. 16, 2009, Office Action. cited by other ; 095107318, Mar. 28, 2008, Office Action (Taiwan). cited by other
- Primary Examiner: Phan, Hanh
- Attorney, Agent or Firm: Workman Nydegger
|
