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- Nachgewiesen in: USPTO Patent Grants
- Sprachen: English
- Patent Number: 8,736,280
- Publication Date: May 27, 2014
- Appl. No: 13/222836
- Application Filed: August 31, 2011
- Assignees: DIT-MCO International Corporation (Kansas City, MO, US)
- Claim: 1. A circuit for testing a high speed data bus, the circuit comprising: a test port coupled to a test controller; a data bus port coupled to the data bus; a signal generator configured to generate a test signal to the data bus port at a first voltage level with a duty cycle of fifty percent or greater; an attenuation monitor configured to receive the test signal from either the signal generator or the data bus port and determine a second voltage level of the received test signal, the second voltage level communicated to the test port; and a polarity monitor configured to receive the test signal from the data bus port, convert the test signal to a direct current polarity voltage which is proportional to the duty cycle and indicative of a polarity of a portion of the data bus, and communicate the polarity voltage to the test port.
- Claim: 2. The circuit of claim 1 , wherein the circuit operates in a plurality of modes including: a first mode in which the signal generator communicates the test signal to the data bus port and to the attenuation monitor, a second mode in which the attenuation monitor receives the test signal from the data bus port, a third mode in which the polarity monitor receives the test signal from the data bus port and communicates the polarity voltage to the test port, and a fourth mode in which the test port is coupled to the data bus port.
- Claim: 3. The circuit of claim 1 , further including a first switching network configured to connect the test port to the polarity monitor, the attenuation monitor, or the data bus port.
- Claim: 4. The circuit of claim 1 , further including a second switching network configured to connect the data bus port to the signal generator, the polarity monitor, the attenuation monitor, or the test port.
- Claim: 5. The circuit of claim 1 , wherein the test signal is a one megahertz square wave with a duty cycle greater than seventy percent.
- Claim: 6. The circuit of claim 1 , wherein the first voltage level is seven volts peak.
- Claim: 7. A circuit for testing a high speed data bus, the circuit comprising: a test port coupled to a test controller; a data bus port coupled to the data bus; a signal generator configured to generate a test signal at a first voltage level with a duty cycle of fifty percent or greater; a polarity monitor configured to receive the test signal and convert the test signal to a direct current polarity voltage which is proportional to the duty cycle and indicative of a polarity of a portion of the data bus; and an attenuation monitor configured to receive the test signal and determine a second voltage level of the received test signal, wherein the circuit operates in a plurality of modes including: a first mode in which the signal generator communicates the test signal to the data bus port and to the attenuation monitor which communicates the second voltage level to the test port, a second mode in which the attenuation monitor receives the test signal from the data bus port and communicates the second voltage level to the test port, a third mode in which the polarity monitor receives the test signal from the data bus port and communicates the polarity voltage to the test port, and a fourth mode in which the test port is coupled to the data bus port.
- Claim: 8. The circuit of claim 7 , further including a first switching network configured to connect the test port to the polarity monitor, the attenuation monitor, or the data bus port.
- Claim: 9. The circuit of claim 7 , further including a second switching network configured to connect the data bus port to the signal generator, the polarity monitor, the attenuation monitor, or the test port.
- Claim: 10. The circuit of claim 7 , wherein the test signal is a one megahertz square wave with a duty cycle greater than seventy percent.
- Claim: 11. The circuit of claim 7 , wherein the first voltage level is seven volts peak.
- Claim: 12. A system for testing a high speed data bus, the system comprising: a first tester circuit coupled to the data bus at a first location and including a signal generator configured to generate a test signal to the data bus at a first voltage level with a duty cycle greater of fifty percent or greater and communicate the first voltage level to a test controller; and a second tester circuit coupled to the data bus at a second location and including: an attenuation monitor configured to receive the test signal, determine a second voltage level of the received test signal, and communicate the second voltage level to the test controller, and a polarity monitor configured to receive the test signal from the data bus port, convert the test signal to a direct current polarity voltage which is proportional to the duty cycle and indicative of a polarity of a portion of the data bus, and communicate the polarity voltage to the test port.
- Claim: 13. The system of claim 12 , wherein the second tester circuit includes a switching network configured to connect either the attenuation monitor or the polarity monitor to the test controller.
- Claim: 14. The system of claim 12 , wherein the test signal is a one megahertz square wave with a duty cycle greater than seventy percent.
- Claim: 15. The system of claim 12 , wherein the first voltage level is seven volts peak.
- Claim: 16. A circuit for testing a high speed data bus, the circuit comprising: a test port coupled to a test controller; a data bus port coupled to the data bus; a signal generator configured to generate a test signal to the data bus port at a first voltage level with a duty cycle of fifty percent or greater; an attenuation monitor configured to receive the test signal from either the signal generator or the data bus port and determine a second voltage level of the received test signal, the second voltage level communicated to the test port; and a polarity monitor configured to receive the test signal from the data bus port, convert the test signal to a direct current polarity voltage which is proportional to the duty cycle and indicative of a polarity of a portion of the data bus, and communicate the polarity voltage to the test port, wherein the circuit operates in a plurality of modes including: a first mode in which the signal generator communicates the test signal to the data bus port and to the attenuation monitor, a second mode in which the attenuation monitor receives the test signal from the data bus port, a third mode in which the polarity monitor receives the test signal from the data bus port and communicates the polarity voltage to the test port, and a fourth mode in which the test port is coupled to the data bus port.
- Current U.S. Class: 324/605
- Patent References Cited: 4213085 July 1980 Ramer ; 5821640 October 1998 Rouchaud ; 2009/0066422 March 2009 Bartlett
- Other References: Portable MIL-STD-1553 databus network tester; precise, rapid & handy, press release issued by Axon Cable SAS on Dec. 4, 2006. cited by examiner ; Alta dt; Data Technolgies; MIL-STD-1553 Tutorial and Reference; Sep. 6, 2007; www.altadt.com. cited by applicant ; MIL-STD-1553 Today and Into the Future; Presented by the IEEE Long Island Section, Instrumentation & Measurement Society on Nov. 13, 2008; DDC Data Device Corporation. cited by applicant
- Assistant Examiner: Miller, Daniel
- Primary Examiner: Koval, Melissa
- Attorney, Agent or Firm: Hovey Williams LLP
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